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general description the MAX9867 is an ultra-low power stereo audio codec designed for portable consumer devices such as mobile phones and portable gaming consoles. the device features stereo differential microphone inputs that can be connected to either analog or digital micro- phones. the single-ended line inputs, with configurable preamplifier, can be sent to the adc for record or routed directly to the headphone amplifier for playback. an aux- iliary adc path can be used to track any dc voltage. the stereo headphone amplifiers support differential, single-ended, and capacitorless output configurations. using the capacitorless output configuration, the device can output 10mw into 32 headphones. comprehensive click-and-pop circuitry suppresses audible clicks and pops during volume changes and startup or shutdown. utilizing maxims proprietary digital circuitry, the device can accept any available 10mhz to 60mhz system clock. this architecture eliminates the need for an external pll and multiple crystal oscillators. the stereo adc and dac paths provide user-configurable voice- band or audioband digital filters. voiceband filters pro- vide extra attenuation at the gsm packet frequency and greater than 70db stopband attenuation at f s/2 . the MAX9867 operates from a single 1.8v supply, and supports a 1.65v to 3.6v logic level. an i 2 c 2-wire seri- al interface provides control for volume levels, signal mixing, and general operating modes. the MAX9867 is available in a tiny 2.2mm x 2.7mm, 0.4mm-ball-pitch, wlp package. a 32-pin 5mm x 5mm tqfn package is also available. features 1.8v single-supply operation 6.7mw playback power consumption 90db stereo dac, 8khz fs 48khz 85db stereo adc, 8khz fs 48khz battery-measurement auxiliary adc support for any master clock between 10mhz to 60mhz stereo digital microphone input support stereo analog differential microphone inputs stereo headphone amplifiers: differential, single-ended, or capacitorless stereo line inputs voiceband filter with a stopband attenuation greater than 70db 1.65v to 3.6v digital interface supply voltage i 2 s/tdm-compatible digital audio bus 30-bump, 2.2mm x 2.7mm 0.4mm-pitch wlp MAX9867 ultra-low power stereo audio codec ________________________________________________________________ maxim integrated products 1 19-4573; rev 0; 4/09 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. ordering information part temp range pin-package MAX9867ewv+ -40c to +85c 30 wlp MAX9867etj+ -40c to +85c 32 tqfn-ep* + denotes lead(pb)-free/rohs-compliant package. *ep = exposed pad. applications cell phones portable gaming devices portable navigation devices portable multimedia players wireless headsets MAX9867 adc audio digital filters dac dac mix mix digital audio interface digital microphone interface control interface headphone amp right mic amp left mic amp left preamp right preamp linein 1 linein 2 headphone amp i 2 c i 2 s/pcm adc simplified block diagram
MAX9867 ultra-low power stereo audio codec 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v avdd = v pvdd = v dvdd = v dvddio = +1.8v, r l = , headphone load (r l ) connected between _outp and _outn in differential mode, c ref = 2.2f, c micbias = c preg = c reg = 1f, av pre = +20db, av pgam = 0db, av dac = 0db, av line = +20db, av vol = 0db, mclk = 13mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) (note 2) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. (voltages with respect to agnd.) dvdd, avdd, and pvdd .........................................-0.3v to +2v dvddio.................................................................-0.3v to +3.6v dgnd and pgnd..................................................-0.1v to +0.1v preg, ref, reg, micbias ....................-0.3v to (avdd + 0.3v) mclk, lrclk, bclk sdout, sdin .................................-0.3v to (dvddio + 0.3v) sda, scl, irq ......................................................-0.3v to +3.6v loutp, loutn, routp, routn .................................(pgnd - 0.3v) to (pvdd + 0.3v) linl, linr, jacksns/aux, miclp/digmicdata, micln/digmicclk, micrp, micrn ..-0.3v to (avdd + 0.3v) continuous power dissipation (t a = +70c) 30-bump wlp (derate 12.5mw/c above +70c) ....1000mw 32-pin tqfn-ep (derate 34.5mw/c above +70c) .2759mw junction-to-ambient thermal resistance ( ja ) (note 1) 30-bump wlp .............................................................80c/w 32-pin tqfn-ep ..........................................................29c/w operating temp range .......................................-40c to +85c storage temp range ........................................-65c to +150c parameter symbol conditions min typ max units pvdd, dvdd, avdd 1.65 1.8 1.95 supply voltage range dvddio 1.65 1.8 3.6 v analog (avdd + pvdd) 4.65 7 full-duplex 8khz mono (voice mode) (note 3) digital (dvdd + dvddio) 0.96 1.5 analog (avdd + pvdd) 3.28 5 dac playback 48khz stereo (audio mode) (note 3) digital (dvdd + dvddio) 1.40 2 analog (avdd + pvdd) 8.0 12 full-duplex 48khz stereo (audio mode) (note 3) digital (dvdd + dvddio) 2.0 3 analog (avdd + pvdd) 3.8 6 total supply current i vdd stereo line-in only digital (dvdd + dvddio) 0.004 0.05 ma analog (avdd + pvdd) 15 shutdown supply current t a = +25c digital (dvdd + dvddio) 15 a note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four- layer board. for detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial .
MAX9867 ultra-low power stereo audio codec _______________________________________________________________________________________ 3 parameter symbol conditions min typ max units shutdown to full operation excludes pll lock time 10 ms soft-start/-stop time 10 ms dac (note 4) master or slave mode 90 dynamic range (note 5) dr f s = 48khz, av vol = +0db, t a = +25c slave mode 84 db differential mode 1 full-scale output v oll /v olr = 0 x 09 capacitorless and single-ended modes 0.56 v rms gain error dc accuracy, measured with respect to full-scale output 15% f s = 8khz 1.2 voice path phase delay p dly f = 1kh z, 0d bfs , h p fi l ter d i sab l ed , d i g i tal i np ut to anal og outp ut f s = 16khz 0.59 ms total harmonic distortion thd mclk = 12.288mhz, f s = 48khz, 0dbfs, measured at headphone outputs -80 db dac attenuation range av dac daca = 0xf to 0x0 -15 0 db dac gain adjust av gain dacg = 00 to 11 0 +18 db v avdd = v pvdd = 1.65v to 1.95v 60 78 f = 217hz, v ripple = 100mv p-p , av vol = 0db 78 f = 1khz, v ripple = 100mv p-p , av vol = 0db 75 power-supply rejection ratio psrr f = 10khz, v ripple = 100mv p-p , av vol = 0db 62 db dac voice mode digital iir lowpass filter with respect to f s within ripple; f s = 8khz to 48khz 0.448 x f s passband cutoff f plp -3db cutoff 0.451 x f s hz passband ripple f < f plp 0.1 db stopband cutoff f slp with respect to f s ; f s = 8khz to 48khz 0.476 x f s hz stopband attenuation f > f slp , f = 20hz to 20khz 75 db electrical characteristics (continued) (v avdd = v pvdd = v dvdd = v dvddio = +1.8v, r l = , headphone load (r l ) connected between _outp and _outn in differential mode, c ref = 2.2f, c micbias = c preg = c reg = 1f, av pre = +20db, av pgam = 0db, av dac = 0db, av line = +20db, av vol = 0db, mclk = 13mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) (note 2)
MAX9867 ultra-low power stereo audio codec 4 _______________________________________________________________________________________ parameter symbol conditions min typ max units dac voice mode digital 5th order iir highpass filter dvflt = 0x1 (elliptical tuned for 16khz gsm + 217hz notch) 0.0161 x f s dvflt = 0x2 (500hz butterworth tuned for 16khz) 0.0312 x f s dvflt = 0x3 (elliptical tuned for 8khz gsm + 217hz notch) 0.0321 x f s dvflt = 0x4 (500hz butterworth tuned for 8khz) 0.0625 x f s 5th order passband cutoff (-3db from peak, i 2 c register programmable) f dhppb dvflt = 0x5 (f s /240 butterworth) 0.0042 x f s hz dvflt = 0x1 (elliptical tuned for 16khz gsm + 217hz notch) 0.0139 x f s dvflt = 0x2 (500hz butterworth tuned for 16khz) 0.0156 x f s dvflt = 0x3 (elliptical tuned for 8khz gsm + 217hz notch) 0.0279 x f s dvflt = 0x4 (500hz butterworth tuned for 8khz) 0.0312 x f s 5th order stopband cutoff (-30db from peak, i 2 c register programmable) f dhpsb dvflt = 0x5 (f s /240 butterworth) 0.0021 x f s hz dc attenuation dc atten dvflt 000 90 db dac stereo audio mode digital fir lowpass filter with respect to f s within ripple; f s = 8khz to 48khz 0.43 x f s -3db cutoff 0.47 x f s passband cutoff f plp -6.02db cutoff 0.50 x f s hz passband ripple f < f plp 0.1 db stopband cutoff f slp with respect to f s ; f s = 8khz to 48khz 0.58 x f s hz stopband attenuation 60 db electrical characteristics (continued) (v avdd = v pvdd = v dvdd = v dvddio = +1.8v, r l = , headphone load (r l ) connected between _outp and _outn in differential mode, c ref = 2.2f, c micbias = c preg = c reg = 1f, av pre = +20db, av pgam = 0db, av dac = 0db, av line = +20db, av vol = 0db, mclk = 13mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) (note 2)
MAX9867 ultra-low power stereo audio codec _______________________________________________________________________________________ 5 parameter symbol conditions min typ max units dac stereo audio mode digital dc blocking highpass filter passband cutoff (-3db from peak) f dhppb dvflt = 0x1 0.000625 x f s hz dc attenuation dc atten dvflt = 0x1 90 db adc (note 6) f s = 8khz, mode = 0 (iir voice) 75 84 dynamic range (note 5) dr f s = 8khz to 48khz, mode = 1 (fir audio) 85 db full-scale input differential mic input or stereo-line inputs, avpre = 0db, avpga = 0db 1v p-p gain error (note 7) dc accuracy, measured with respect to 80% of full-scale output 15% f s = 8khz 1.2 voice path phase delay p dly f = 1khz, 0dbfs, hp filter disabled, analog input to digital output f s = 16khz 0.61 ms total harmonic distortion thd f = 1khz, f s = 8khz, t a = +25c, 0dbfs -81 -70 db adc level adjust range av adc avl/vr = 0xf to 0x0 -12 +3 db v avdd = 1.65v to 1.95v, input referred 60 85 f = 217hz, v ripple = 100mv, av adc = 0db, input referred 85 f = 1khz, v ripple = 100mv, av adc = 0db, input referred 80 power-supply rejection ratio psrr f = 10khz, v ripple = 100mv, av adc = 0db, input referred 80 db adc voice mode digital iir lowpass filter with respect to f s within ripple; f s = 8khz to 48khz 0.445 x f s passband cutoff f plp -3db cutoff 0.449 x f s hz passband ripple f < f plp 0.1 db stopband cutoff f slp with respect to f s ; f s = 8khz to 48khz 0.469 x f s hz stopband attenuation f > f slp , f = 20hz to 20khz 74 db electrical characteristics (continued) (v avdd = v pvdd = v dvdd = v dvddio = +1.8v, r l = , headphone load (r l ) connected between _outp and _outn in differential mode, c ref = 2.2f, c micbias = c preg = c reg = 1f, av pre = +20db, av pgam = 0db, av dac = 0db, av line = +20db, av vol = 0db, mclk = 13mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) (note 2)
MAX9867 ultra-low power stereo audio codec 6 _______________________________________________________________________________________ parameter symbol conditions min typ max units adc voice mode digital 5th order iir highpass filter avflt = 0x1 (elliptical tuned for 16khz gsm + 217hz notch) 0.0161 x f s avflt = 0x2 (500hz butterworth tuned for 16khz) 0.0312 x f s avflt = 0x3 (elliptical tuned for 8khz gsm + 217hz notch) 0.0321 x f s avflt = 0x4 (500hz butterworth tuned for 8khz) 0.0625 x f s 5th order passband cutoff (-3db from peak, i 2 c register programmable) f ahppb avflt = 0x5 (f s /240 butterworth) 0.0042 x f s hz avflt = 0x1 (elliptical tuned for 16khz gsm + 217hz notch) 0.0139 x f s avflt = 0x2 (500hz butterworth tuned for 16khz) 0.0156 x f s avflt = 0x3 (elliptical tuned for 8khz gsm + 217hz notch) 0.0279 x f s avflt = 0x4 (500hz butterworth tuned for 8khz) 0.0312 x f s stopband cutoff (-30db from peak) f ahpsb avflt = 0x5 (f s /240 butterworth) 0.0021 x f s hz dc attenuation dc atten avflt 000 90 db adc stereo audio mode digital fir lowpass filter with respect to f s within ripple; f s = 8khz to 48khz 0.43 x f s -3db cutoff 0.48 x f s passband cutoff f plp -6.02db cutoff 0.5 x f s hz passband ripple f < f plp 0.1 db stopband cutoff f slp with respect to f s ; f s = 8khz to 48khz 0.58 x f s hz stopband attenuation f > f slp , f = 20hz to 20khz 60 db electrical characteristics (continued) (v avdd = v pvdd = v dvdd = v dvddio = +1.8v, r l = , headphone load (r l ) connected between _outp and _outn in differential mode, c ref = 2.2f, c micbias = c preg = c reg = 1f, av pre = +20db, av pgam = 0db, av dac = 0db, av line = +20db, av vol = 0db, mclk = 13mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) (note 2)
MAX9867 ultra-low power stereo audio codec _______________________________________________________________________________________ 7 parameter symbol conditions min typ max units adc stereo audio mode digital dc blocking highpass filter passband cutoff (-3db from peak) f ahppb avflt = 0x1 0.000625 x f s hz dc attenuation dc atten avflt = 0x1 90 db output volume control voll/volr = 0x00 14.55 14.9 15.15 voll/volr = 0x01 14.1 14.4 14.6 voll/volr = 0x02 13.6 13.9 14.1 voll/volr = 0x04 12.6 12.9 13.1 voll/volr = 0x08 9.35 9.9 10.35 voll/volr = 0x10 0.35 0.9 1.35 line input to output volume control av vol voll/volr = 0x20 -50.15 -49.2 -48.15 db voll/volr = 0x00 to 0x06 (+6db to +3db) 0.5 voll/volr = 0x06 to 0x0f (+3db to -6db) 1 voll/volr = 0x0f to 0x17 (-6db to -22db) 2 output volume control step size v o ll/v o lr = 0x17 to 0x3f ( - 22d b to m ute) 4 db output volume control mute attenuation f = 1khz 100 db headphone amplifier (note 8) r l = 16 30 52 output power per channel (differential mode) p out f = 1khz, thd < 1%, t a = +25c r l = 32 32 mw r l = 16 19 output power per channel (capacitorless mode) p out f = 1khz, thd < 1%, t a = +25c r l = 32 810 mw r l = 16 , p out = 25mw, f = 1khz -76 mclk = 13mhz, f s = 8khz -77 -70 total harmonic distortion + noise (differential mode) thd+n r l = 32 , p out = 25mw, f = 1khz mclk = 12.288mhz, f s = 48khz -80 db r l = 16 , p out = 6.25mw, f = 1khz -72 mclk = 13mhz, f s = 8khz -74 -65 total harmonic distortion + noise (capacitorless mode) thd+n r l = 32 , p out = 6.25mw, f = 1khz mclk = 12.288mhz, f s = 48khz -74 db r l = 16 , p out = 6.25mw, f = 1khz -74 mclk = 13mhz, f s = 8khz -74 -65 total harmonic distortion + noise (se mode) thd+n r l = 32 , p out = 6.25mw, f = 1khz mclk = 12.288mhz, f s = 48khz -76 db dynamic range dr av vol = +6db (notes 5, 7) 76 90 db electrical characteristics (continued) (v avdd = v pvdd = v dvdd = v dvddio = +1.8v, r l = , headphone load (r l ) connected between _outp and _outn in differential mode, c ref = 2.2f, c micbias = c preg = c reg = 1f, av pre = +20db, av pgam = 0db, av dac = 0db, av line = +20db, av vol = 0db, mclk = 13mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) (note 2)
MAX9867 ultra-low power stereo audio codec 8 _______________________________________________________________________________________ parameter symbol conditions min typ max units v avdd = v pvdd = 1.65v to 1.95v 60 78 f = 217hz, v ripple = 100mv p-p , av vol = 0db 78 f = 1khz, v ripple = 100mv p-p , av vol = 0db 75 power-supply rejection ratio (note 7) psrr f = 10khz, v ripple = 100mv p-p , av vol = 0db 62 db av vol = -84db differential mode (loutpCloutn, routpCroutn), t a = +25c 0.2 1.3 output offset voltage v os av vol = -84db capacitorless mode (loutpCloutn, routpCloutn), t a = +25c 0.8 3 mv differential mode, p out = 5mw, f = 1khz 87 tqfn 55 crosstalk x talk capacitorless mode, p out = 5mw, f = 1khz wlp 60 db r l = 32 500 capacitive drive no sustained oscillations r l = 100 pf into shutdown -80 click-and-pop level (differential, capacitorless modes) peak voltage, a-weighted, 32 samples per second out of shutdown -69 dbv into shutdown -75 click-and-pop level (se mode) peak voltage, a-weighted, 32 samples per second out of shutdown -75 dbv microphone amplifier palen/paren = 01 -0.5 0 +0.5 palen/paren = 10 19.5 20 20.5 preamplifier gain av pre palen/paren = 11 29.5 30 30.5 db pgaml/pgamr = 0x1f -0.6 -0.1 +0.4 mic pga gain av pgam pgaml/pgamr = 0x00 19.3 19.75 20.3 db common-mode rejection ratio cmrr v in = 100mv p-p , f = 217hz 50 db mic input resistance r in_mic all gain settings 30 50 k electrical characteristics (continued) (v avdd = v pvdd = v dvdd = v dvddio = +1.8v, r l = , headphone load (r l ) connected between _outp and _outn in differential mode, c ref = 2.2f, c micbias = c preg = c reg = 1f, av pre = +20db, av pgam = 0db, av dac = 0db, av line = +20db, av vol = 0db, mclk = 13mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) (note 2)
MAX9867 ultra-low power stereo audio codec _______________________________________________________________________________________ 9 parameter symbol conditions min typ max units av pre = 0db, v in = 1v p-p , f = 1khz -80 total harmonic distortion + noise thd+n av pre = +30db, v in = 32mv p-p , f = 1khz, (1v p-p at adc input) -67 db v avdd = 1.65v to 1.95v, input referred 60 85 f = 217hz, v ripple = 100mv, av adc = 0db, input referred 85 f = 1khz, v ripple = 100mv, av adc = 0db, input referred 80 power-supply rejection ratio psrr f = 10khz, v ripple = 100mv, av adc = 0db, input referred 80 db microphone bias output voltage v micbias v avdd = 1.8v, i load = 1ma 1.5 1.525 1.55 v load regulation i load = 1ma to 2ma 0.2 10 v/a line regulation v avdd = 1.65v to 1.95v 10 v/v f = 217hz, v ripple = 100mv p-p 85 power-supply rejection ratio psrr f = 10khz, v ripple = 100mv p-p 81 db noise voltage a-weighted 9.1 v rms line input full-scale input v in av line = 0db 1.0 v p-p line input level adjust range av line ligl/ligr = 0xf to 0x0 -6.5 +24.5 db line input mute attenuation f = 1khz 100 db input resistance r in_line av line = +24db 20 k total harmonic distortion + noise thd+n v in = 0.1v p-p , f = 1khz, differential output -83 db auxin input input dc voltage range auxen = 1 0 0.738 v auxin input resistance rin auxen = 1, 0v auxin 0.738 10 40 m jack sense operation jdeten = 1, shdn = 1, jacksns 0.92 x micbias 0.95 x micbias 0.98 x micbias threshold vth jdeten = 1, shdn = 0, jacksns, loutp avdd - 0.8 avdd - 0.4 avdd - 0.15 v jdeten = 1, shdn = 1, jacksns = gnd 4 pullup current ipu jdeten = 1, shdn = 0, jacksns = loutp = gnd 420 a pullup voltage jdeten = 1, jacksns, loutp avdd v electrical characteristics (continued) (v avdd = v pvdd = v dvdd = v dvddio = +1.8v, r l = , headphone load (r l ) connected between _outp and _outn in differential mode, c ref = 2.2f, c micbias = c preg = c reg = 1f, av pre = +20db, av pgam = 0db, av dac = 0db, av line = +20db, av vol = 0db, mclk = 13mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) (note 2)
MAX9867 ultra-low power stereo audio codec 10 ______________________________________________________________________________________ electrical characteristics (continued) (v avdd = v pvdd = v dvdd = v dvddio = +1.8v, r l = , headphone load (r l ) connected between _outp and _outn in differential mode, c ref = 2.2f, c micbias = c preg = c reg = 1f, av pre = +20db, av pgam = 0db, av dac = 0db, av line = +20db, av vol = 0db, mclk = 13mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) (note 2) parameter symbol conditions min typ max units digital sidetone sidetone gain adjust range av stga differential output mode, dvst = 0x1f to 0x01 -60 0 db voice path phase delay p dly mic input to headphone output, f = 1khz, hp filter disabled, f s = 8khz 2.2 ms input clock characteristics mclk input frequency f mclk for any lrclk sample rate 10 60 mhz prescaler = /1 mode 40 60 mclk input duty cycle /2 or /4 modes 30 70 % maximum mclk input jitter maximum allowable rms for performance limits 100 ps rms lrclk sample rate range 8 48 khz rapid lock mode 2 7 lrclk pll lock time any allowable lrclk and pclk rate, slave mode nonrapid lock mode 12 25 ms lrclk acceptable jitter for maintaining pll lock allowable lrclk period change from nominal for slave pll mode at any allowable lrclk and pclk rates 100 ns freq = 0x8 through 0xf 0 0 % pclk = 192xf s , 256xf s , 384xf s , 512xf s , 768xf s , and 1024xf s 00 lrclk average frequency error (master and slave modes) (note 9) all other modes -0.025 +0.025 digital input (mclk) input high voltage v ih 1.2 v input low voltage v il 0.6 v input leakage current i ih , i il t a = +25c 1 a input capacitance 10 pf digital inputs (sdin, bclk, lrclk) input high voltage v ih 0.7 x dvddio v input low voltage v il 0.3 x dvddio v input hysteresis 200 mv input leakage current i ih , i il t a = +25c 1 a input capacitance 10 pf
MAX9867 ultra-low power stereo audio codec ______________________________________________________________________________________ 11 electrical characteristics (continued) (v avdd = v pvdd = v dvdd = v dvddio = +1.8v, r l = , headphone load (r l ) connected between _outp and _outn in differential mode, c ref = 2.2f, c micbias = c preg = c reg = 1f, av pre = +20db, av pgam = 0db, av dac = 0db, av line = +20db, av vol = 0db, mclk = 13mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) (note 2) parameter symbol conditions min typ max units digital inputs (sda, scl) input high voltage v ih 0.7 x dvdd v input low voltage v il 0.3 x dvdd v input hysteresis 200 mv input leakage current i ih , i il t a = +25c 1 a input capacitance 10 pf digital input (digmicdata) input high voltage v ih 0.65 x dvdd v input low voltage v il 0.35 x dvdd v input hysteresis 100 mv input leakage current i ih , i il t a = +25c 35 a input capacitance 10 pf cmos digital outputs (bclk, lrclk, sdout) output low voltage v ol i ol = 3ma 0.4 v output high voltage v oh i oh = 3ma dvddio - 0.4 v cmos digital output (digmicclk) output low voltage v ol i ol = 1ma 0.4 v output high voltage v oh i oh = 1ma dvdd - 0.4 v open-drain digital outputs (sda, irq ) output high current i oh v out = dvdd, t a = +25c 1 a output low voltage v ol i ol = 3ma 0.2 x dvdd v digital microphone timing characteristics (v dvdd = 1.65v) micclk = 00 pclk/8 digmicclk divide ratio f micclk micclk = 01 pclk/6 mhz digmicdata to digmicclk setup time t su,mic either clock edge 20 ns digmicdata to digmicclk hold time t hd , mic either clock edge 0 ns digital audio interface timing characteristics (v dvdd = 1.65v) t bclks slave operation 75 ns minimum bclk cycle time t bclkm master operation 325 ns
MAX9867 ultra-low power stereo audio codec 12 ______________________________________________________________________________________ parameter symbol conditions min typ max units minimum bclk high time t bclkh slave operation 30 ns minimum bclk low time t bclkl slave operation 30 ns bclk or lrclk rise and fall t r , t f master operation, c l = 15pf 7 ns sdin or lrclk to bclk setup time t su 20 ns sdin or lrclk to bclk hold time t hd 0ns sdout delay time from bclk rising edge t dly c l = 30pf 0 40 ns i 2 c timing characteristics (v dvdd = 1.65v) serial-clock frequency f scl 0 400 khz bus free time between stop and start conditions t buf 1.3 s hold time (repeated) start condition t hd , sta 0.6 s scl pulse-width low t low 1.3 s scl pulse-width high t high 0.6 s setup time for a repeated start condition t su,sta 0.6 s data hold time t hd , dat r pu,sda = 475 0 900 ns data setup time t su , dat 100 ns sda and scl receiving rise time t r (note 10) 20 + 0.1c b 300 ns sda and scl receiving fall time t f (note 10) 20 + 0.1c b 300 ns sda transmitting fall time t f r pu,sda = 475 (note 10) 20 + 0.1c b 250 ns setup time for stop condition t su , sto 0.6 s bus capacitance c b 400 pf pulse width of suppressed spike t sp 050ns note 2: the MAX9867 is 100% production tested at t a = +25?. specifications over temperature limits are guaranteed by design. note 3: clocking all zeros into the dac, master mode, and differential headphone mode. note 4: dac performance measured at the headphone outputs. note 5: dynamic range measured using the eiaj method. -60dbfs 1khz output signal, a-weighted, and normalized to 0dbfs. f = 20hz to 20khz. note 6: performance measured using microphone inputs, unless otherwise stated. note 7: performance measured using line inputs. note 8: performance measured using dac, unless otherwise stated. lrclk = 8khz, unless otherwise stated. note 9: in master-mode operation, the accuracy of the mclk input proportionally determines the accuracy of the sample clock rate. note 10: c b is in pf. electrical characteristics (continued) (v avdd = v pvdd = v dvdd = v dvddio = +1.8v, r l = , headphone load (r l ) connected between _outp and _outn in differential mode, c ref = 2.2f, c micbias = c preg = c reg = 1f, av pre = +20db, av pgam = 0db, av dac = 0db, av line = +20db, av vol = 0db, mclk = 13mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) (note 2)
MAX9867 ultra-low power stereo audio codec ______________________________________________________________________________________ 13 total harmonic distortion + noise vs. power out (dac to headphone) MAX9867 toc01 power out (mw) thd+n (db) 1510 30 52 5 20 -50 -40 -30 -80 -70 -60 -20 -10 0 -90 03 5 mclk = 13mhz lrclk = 8khz r load = 32 differential mode 3khz 20hz 1khz total harmonic distortion + noise vs. power out (dac to headphone) MAX9867 toc02 power out (mw) thd+n (db) 5040 2010 30 60 -50 -40 -30 -80 -70 -60 -20 -10 0 -90 0 mclk = 13mhz lrclk = 8khz r load = 16 differential mode 3khz 20hz 1khz total harmonic distortion + noise vs. power out (dac to headphone) MAX9867 toc03 power out (mw) thd+n (db) 1510 30 52 5 20 -50 -40 -30 -80 -70 -60 -20 -10 0 -90 03 5 mclk = 12.288mhz lrclk = 48khz r load = 32 differential mode 6khz 20hz 1khz typical operating characteristics (v avdd = v dvdd = v pvdd = +1.8v, c ref = 2.2?, c micbias = c preg = c reg = 1?, av micpga = 0db, mclk = 13mhz, lrclk = 8khz, bw = 20hz to f s /2, t a = +25?, unless otherwise noted.) total harmonic distortion + noise vs. power out (dac to headphone) MAX9867 toc04 power out (mw) thd+n (db) 5040 2010 30 60 -50 -40 -30 -80 -70 -60 -20 -10 0 -90 0 mclk = 12.288mhz lrclk = 48khz r load = 16 differential mode 6khz 20hz 1khz total harmonic distortion + noise vs. frequency (dac to headphone) MAX9867 toc05 frequency (hz) thd+n (%) 1000 100 -50 -40 -30 -80 -70 -60 -20 -10 0 -90 10 10,000 mclk = 13mhz lrclk = 8khz r load = 32 differential mode 5mw 20mw total harmonic distortion + noise vs. frequency (dac to headphone) MAX9867 toc06 frequency (hz) thd+n (%) 1000 100 -50 -40 -30 -80 -70 -60 -20 -10 0 -90 10 10,000 mclk = 13mhz lrclk = 8khz r load = 16 differential mode 5mw 20mw total harmonic distortion + noise vs. frequency (dac to headphone) MAX9867 toc07 frequency (hz) thd+n (%) 100 10,000 -50 -40 -30 -80 -70 -60 -20 -10 0 -90 10 1000 100,000 mclk = 12.288mhz lrclk = 48khz r load = 32 differential mode 5mw 20mw total harmonic distortion + noise vs. frequency (dac to headphone) MAX9867 toc08 frequency (hz) thd+n (%) 100 10,000 -50 -40 -30 -80 -70 -60 -20 -10 0 -90 10 1000 100,000 mclk = 12.288mhz lrclk = 48khz r load = 16 differential mode 5mw 20mw total harmonic distortion + noise vs. power out (dac to headphone) MAX9867 toc09 power out (mw) thd+n (db) 41 0 68 2 -50 -40 -30 -80 -70 -60 -20 -10 0 -90 0 mclk = 13mhz lrclk = 8khz r load = 32 capacitorless mode 3khz 20hz 1khz
MAX9867 ultra-low power stereo audio codec 14 ______________________________________________________________________________________ total harmonic distortion + noise vs. power out (dac to headphone) MAX9867 toc10 power out (mw) thd+n (db) 810 4 212 6 -50 -40 -30 -80 -70 -60 -20 -10 0 -90 0 mclk = 12.288mhz lrclk = 48khz r load = 32 capacitorless mode 6khz 20hz 1khz total harmonic distortion + noise vs. frequency (dac to headphone) MAX9867 toc11 frequency (hz) thd+n (%) 1000 100 -50 -40 -30 -80 -70 -60 -20 -10 0 -90 10 10,000 mclk = 13mhz lrclk = 8khz r load = 32 capacitorless mode 1mw 5mw total harmonic distortion + noise vs. frequency (dac to headphone) MAX9867 toc12 frequency (hz) thd+n (%) 100 10,000 -50 -40 -30 -80 -70 -60 -20 -10 0 -90 10 1000 100,000 mclk = 12.288mhz lrclk = 48khz r load = 32 capacitorless mode 1mw 5mw total harmonic distortion + noise vs. power out (dac to headphone) MAX9867 toc13 power out (mw) thd+n (db) 410 68 2 -50 -40 -30 -80 -70 -60 -20 -10 0 -90 0 mclk = 13mhz lrclk = 8khz r load = 32 , c out = 220 f single-ended mode 3khz 20hz 1khz total harmonic distortion + noise vs. power out (dac to headphone) MAX9867 toc14 power out (mw) thd+n (db) 810 4 26 12 -50 -40 -30 -80 -70 -60 -20 -10 0 -90 0 mclk = 12.288mhz lrclk = 48khz r load = 32 , c out = 220 f single-ended mode 6khz 20hz 1khz total harmonic distortion + noise vs. frequency (dac to headphone) MAX9867 toc15 frequency (hz) thd+n (%) 1000 100 -50 -40 -30 -80 -70 -60 -20 -10 0 -90 10 10,000 mclk = 13mhz lrclk = 8khz r load = 32 , c out = 220 f single-ended mode p out specified at 1khz 1mw 5mw total harmonic distortion + noise vs. frequency (dac to headphone) MAX9867 toc16 frequency (hz) thd+n (%) 100 10,000 -50 -40 -30 -80 -70 -60 -20 -10 0 -90 10 1000 100,000 mclk = 13mhz lrclk = 8khz r load = 32 , c out = 220 f single-ended mode p out specified at 1khz 1mw 5mw total harmonic distortion + noise vs. power out (line in to headphone) MAX9867 toc17 power out (mw) thd+n (db) 40 25 15 20 10 45 35 30 5 -50 -40 -30 -70 -60 -20 -10 0 -80 050 line in preamp = +18db r load = 32 differential mode 6khz 20hz 1khz total harmonic distortion + noise vs. power out (line in to headphone) MAX9867 toc18 power out (mw) thd+n (db) 25 10 20 35 30 15 5 -50 -40 -30 -70 -80 -60 -20 -10 0 -90 040 line in preamp = 0db r load = 32 differential mode 1khz 6khz 20hz typical operating characteristics (continued) (v avdd = v dvdd = v pvdd = +1.8v, c ref = 2.2f, c micbias = c preg = c reg = 1f, av micpga = 0db, mclk = 13mhz, lrclk = 8khz, bw = 20hz to f s /2, t a = +25c, unless otherwise noted.)
MAX9867 ultra-low power stereo audio codec ______________________________________________________________________________________ 15 total harmonic distortion + noise vs. frequency (line in to headphone) MAX9867 toc19 frequency (hz) thd+n (db) 100 10,000 -50 -40 -30 -80 -70 -60 -20 -10 0 -90 10 1000 100,000 line in preamp = +18db r load = 32 differential mode 5mw 20mw total harmonic distortion + noise vs. frequency (line in to headphone) MAX9867 toc20 frequency (hz) thd+n (db) 100 10,000 -50 -40 -30 -80 -70 -60 -20 -10 0 -90 10 1000 100,000 line in preamp = +18db r load = 32 differential mode 5mw 20mw power out vs. headphone load MAX9867 toc21 headphone load ( ) power out (mw) 10 40 50 10 20 30 60 0 1 100 1000 mclk = 12.288mhz lrclk = 48khz thd+n = < 0.1% differential mode power out vs. headphone load MAX9867 toc22 headphone load ( ) power out (mw) 10 20 25 5 10 15 30 0 1 100 1000 mclk = 12.288mhz lrclk = 48khz thd+n = < 0.1% capacitorless mode power out vs. headphone load MAX9867 toc23 headphone load ( ) power out (mw) 10 20 5 10 15 25 0 1 100 1000 mclk = 12.288mhz lrclk = 48khz thd+n = < 0.1% single-ended mode total harmonic distortion + noise vs. frequency (microphone to adc) MAX9867 toc24 frequency (hz) thd+n (%) 1000 100 -50 -40 -30 -80 -70 -60 -20 -10 0 -90 10 10,000 mclk = 13mhz lrclk = 8khz micpre = 0db v in = 1v p-p total harmonic distortion + noise vs. frequency (microphone to adc) MAX9867 toc25 frequency (hz) thd+n (%) 1000 100 -50 -40 -30 -80 -70 -60 -20 -10 0 -90 10 10,000 mclk = 13mhz lrclk = 8khz micpre = 20db v in = 0.11v p-p total harmonic distortion + noise vs. frequency (microphone to adc) MAX9867 toc26 frequency (hz) thd+n (%) 1000 100 -50 -40 -30 -80 -70 -60 -20 -10 0 -90 10 10,000 mclk = 13mhz lrclk = 8khz micpre = 30db v in = 0.032v p-p power-supply rejection ratio vs. frequency (dac to headphone) MAX9867 toc27 frequency (hz) psrr (db) 100 10,000 -50 -40 -30 -80 -70 -60 -20 -10 0 -90 10 1000 100,000 v ripple = 100mv p-p mclk = 13mhz lrclk = 8khz typical operating characteristics (continued) (v avdd = v dvdd = v pvdd = +1.8v, c ref = 2.2f, c micbias = c preg = c reg = 1f, av micpga = 0db, mclk = 13mhz, lrclk = 8khz, bw = 20hz to f s /2, t a = +25c, unless otherwise noted.)
MAX9867 ultra-low power stereo audio codec 16 ______________________________________________________________________________________ power-supply rejection ratio vs. frequency (mic to adc) MAX9867 toc28 frequency (hz) psrr (db) -50 -40 -30 -80 -70 -60 -20 -10 0 -90 10 100 1000 v ripple = 100mv p-p mclk = 13mhz lrclk = 8khz power-supply rejection ratio vs. frequency (micbias) MAX9867 toc29 frequency (hz) psrr (db) -50 -40 -30 -80 -70 -60 -20 -10 0 -90 10 100 1000 v ripple = 100mv p-p fft, dac to headphone, 0dbfs, mclk = 13mhz, lrclk = 8khz MAX9867 toc30 amplitude (db) -60 -40 -120 -100 -80 -20 0 20 -140 061218 freq = 0xa frequency (khz) 20 281016 414 fft, dac to headphone, -60dbfs, mclk = 13mhz, lrclk = 8khz MAX9867 toc31 amplitude (db) -60 -40 -120 -100 -80 -20 0 20 -140 freq = 0xa 0 6 12 18 frequency (khz) 20 2 8 10 16 414 fft, dac to headphone, 0dbfs, mclk = 12.288mhz, lrclk = 48khz MAX9867 toc32 amplitude (db) -60 -40 -120 -100 -80 -20 0 20 -140 ni = 6000 0 6 12 18 frequency (khz) 20 2 8 10 16 414 fft, dac to headphone, -60dbfs, mclk = 12.288mhz, lrclk = 48khz MAX9867 toc33 amplitude (db) -60 -40 -120 -100 -80 -20 0 20 -140 ni = 6000 061218 frequency (khz) 20 281016 414 fft, dac to headphone, 0dbfs, mclk = 13mhz, lrclk = 48khz MAX9867 toc34 amplitude (db) -60 -40 -120 -100 -80 -20 0 20 -140 pll mode 0 6 12 18 frequency (khz) 20 2 8 10 16 414 fft, dac to headphone, -60dbfs, mclk = 13mhz, lrclk = 48khz MAX9867 toc35 amplitude (db) -60 -40 -120 -100 -80 -20 0 20 -140 pll mode 0 6 12 18 frequency (khz) 20 2 8 10 16 414 fft, dac to headphone, 0dbfs, mclk = 13mhz, lrclk = 44.1khz MAX9867 toc36 amplitude (db) -60 -40 -120 -100 -80 -20 0 20 -140 pll mode 061218 frequency (khz) 20 281016 414 typical operating characteristics (continued) (v avdd = v dvdd = v pvdd = +1.8v, c ref = 2.2f, c micbias = c preg = c reg = 1f, av micpga = 0db, mclk = 13mhz, lrclk = 8khz, bw = 20hz to f s /2, t a = +25c, unless otherwise noted.)
MAX9867 ultra-low power stereo audio codec ______________________________________________________________________________________ 17 fft, dac to headphone, -60dbfs, mclk = 13mhz, lrclk = 44.1khz MAX9867 toc37 amplitude (db) -60 -40 -120 -100 -80 -20 0 20 -140 pll mode 0 6 12 18 frequency (khz) 20 2 8 10 16 414 fft, microphone to adc, 0dbfs, mclk = 13mhz, lrclk = 8khz MAX9867 toc38 frequency (hz) amplitude (db) 1000 3000 -60 -40 -20 -120 -100 -80 0 20 -140 0 2000 4000 500 2500 1500 3500 freq = 0xa fft, microphone to adc, -60dbfs, mclk = 13mhz, lrclk = 8khz MAX9867 toc39 frequency (hz) amplitude (db) 1000 3000 -60 -40 -20 -120 -100 -80 0 20 -140 0 2000 4000 500 2500 1500 3500 freq = 0xa fft, microphone to adc, 0dbfs, mclk = 12.288mhz, lrclk = 48khz MAX9867 toc40 amplitude (db) -60 -40 -120 -100 -80 -20 0 20 -140 ni = 6000 0 6 12 18 frequency (khz) 20 2 8 10 16 414 fft, microphone to adc, -60dbfs, mclk = 12.288mhz, lrclk = 48khz MAX9867 toc41 amplitude (db) -60 -40 -120 -100 -80 -20 0 20 -140 ni = 6000 0 6 12 18 frequency (khz) 20 2 8 10 16 414 fft, microphone to adc, 0dbfs, mclk = 13mhz, lrclk = 48khz MAX9867 toc42 amplitude (db) -60 -40 -120 -100 -80 -20 0 20 -140 pll mode 061218 frequency (khz) 20 281016 414 fft, microphone to adc, -60dbfs, mclk = 13mhz, lrclk = 48khz MAX9867 toc43 amplitude (db) -60 -40 -120 -100 -80 -20 0 20 -140 pll mode 0 6 12 18 frequency (khz) 20 2 8 10 16 414 wideband fft, dac to headphone, 0dbfs, mclk = 13mhz, lrclk = 8khz MAX9867 toc44 frequency (khz) amplitude (db) 40 100 -60 -40 -20 -120 -100 -80 0 -140 0 60 120 20 80 freq = 0xa wideband fft, dac to headphone, -60dbfs, mclk = 13mhz, lrclk = 8khz MAX9867 toc45 frequency (khz) amplitude (db) 40 100 -60 -40 -20 -120 -100 -80 0 20 -140 060120 20 80 freq = 0xa typical operating characteristics (continued) (v avdd = v dvdd = v pvdd = +1.8v, c ref = 2.2f, c micbias = c preg = c reg = 1f, av micpga = 0db, mclk = 13mhz, lrclk = 8khz, bw = 20hz to f s /2, t a = +25c, unless otherwise noted.)
MAX9867 ultra-low power stereo audio codec 18 ______________________________________________________________________________________ dac iir highpass filter frequency response, mode = 0 MAX9867 toc46 frequency (hz) amplitude (db) 220 520 320 420 120 -40 0 -20 -80 -60 20 -100 20 dvflt = 0 dvflt = 3 dvflt = 4 lrclk = 8khz mode = 0 dac iir highpass filter frequency response, mode = 0 MAX9867 toc47 frequency (hz) amplitude (db) 220 520 320 420 120 -40 0 -20 -80 -60 20 -100 20 avflt = 0 avflt = 3 avflt = 4 lrclk = 8khz dac iir/fir lowpass filter frequency response (8khz) MAX9867 toc48 amplitude (db) -30 0 -20 -70 -50 10 -10 -60 -40 20 -80 mode = 0 mode = 1 3.0 3.3 3.6 3.9 frequency (khz) 4.0 3.1 3.4 3.5 3.8 3.2 3.7 adc iir/fir lowpass filter frequency response (8khz) MAX9867 toc49 amplitude (db) -40 10 -20 -80 -60 20 -100 mode = 0 mode = 1 3.0 3.3 3.6 3.9 frequency (khz) 4.0 3.1 3.4 3.5 3.8 3.2 3.7 shutdown to dac full operation (capacitorless or differential mode) MAX9867 toc50 time (4ms/div) loutp (500mv/div) scl (2v/div) shutdown to dac full operation (clickless single-ended mode) MAX9867 toc51 time (40ms/div) loutp (500mv/div) scl (2v/div) shutdown to dac full operation (fast turn-on single-ended mode) MAX9867 toc52 time (4ms/div) loutp (500mv/div) scl (2v/div) typical operating characteristics (continued) (v avdd = v dvdd = v pvdd = +1.8v, c ref = 2.2f, c micbias = c preg = c reg = 1f, av micpga = 0db, mclk = 13mhz, lrclk = 8khz, bw = 20hz to f s /2, t a = +25c, unless otherwise noted.)
MAX9867 ultra-low power stereo audio codec ______________________________________________________________________________________ 19 full operation to shutdown (dac) MAX9867 toc53 time (1ms/div) loutp (500mv/div) scl (2v/div) adc soft-start MAX9867 toc54 time (4ms/div) adc out (500mv/div) scl (2v/div) total harmonic distortion + noise vs. mclk frequency, 0dbfs MAX9867 toc55 mclk frequency (mhz) thd+n (db) 20 15 40 50 25 55 45 -50 -40 -30 -80 -90 -70 -60 -20 -10 0 -100 10 60 30 35 lrclk = 48khz pll mode dynamic range vs. mclk frequency MAX9867 toc56 mclk frequency (mhz) dynamic range (db) 90 100 70 80 110 120 60 10 100 v in = -60dbfs lrclk = 48khz pll mode a-weighted line input resistance vs. gain setting MAX9867 toc57 gain setting (db) input resistance (k ) 170 220 70 120 270 20 -6 4 14 24 -1 9 19 aux code vs. input voltage MAX9867 toc58 input voltage (v) aux code (signed decimal) 20,000 25,000 10,000 15,000 0 5000 30,000 -5000 -0.4 0.8 0.2 1.2 0.6 0.4 01.0 -0.2 typical operating characteristics (continued) (v avdd = v dvdd = v pvdd = +1.8v, c ref = 2.2f, c micbias = c preg = c reg = 1f, av micpga = 0db, mclk = 13mhz, lrclk = 8khz, bw = 20hz to f s /2, t a = +25c, unless otherwise noted.)
MAX9867 ultra-low power stereo audio codec 20 ______________________________________________________________________________________ pin description pin/bump tqfn-ep wlp name function 1 a2 dgnd digital ground 2 b3 scl i 2 c serial-clock input. connect a pullup resistor to a 1.7v to 3.3v supply. 3 a3 sda i 2 c serial-data input/output. connect a pullup resistor to a 1.7v to 3.3v supply. 4c3 irq hardware interrupt output. irq can be programmed to pull low when bits in status register 0x00 are set. read status register 0x00 to clear irq once set. repeat faults have no effect on irq until it is cleared by reading register 0x00. connect a 10k pullup resistor to a 1.7v to 3.3v supply. 5 a4 avdd analog power supply. bypass to agnd with a 1f capacitor. 6 b4 ref converter reference. bypass to agnd with a 2.2f capacitor (1.23v nominal). 7 a5 preg positive internal regulated supply. bypass to agnd with a 1f capacitor (1.6v nominal). 8 b5 reg preg/2 voltage reference. bypass to agnd with a 1f capacitor (0.8v nominal). 9 a6 agnd analog ground 10 b6 micbias low-noise microphone bias. connect a 2.2k to 470 resistor to the positive output of a microphone (1.525v nominal). bypass to agnd with a 1f capacitor. 11 c5 micln/ digmicclk left negative differential microphone input or digital microphone clock output. for analog microphones, ac-couple to the negative output of a microphone with a 1f capacitor. for digital microphones, connect to the clock input of the microphone. 12 c6 miclp/ digmicdata left positive differential microphone input or digital microphone data input. for analog microphones, ac-couple to the positive output of a microphone with a 1f capacitor. for digital microphones, connect to the data output of the microphone(s). up to two digital microphones can be connected. 13 c4 micrp right positive differential microphone input. ac-couple to the positive output of a microphone with a 1f capacitor. 14 d6 micrn right negative differential microphone input. ac-couple to the negative output of a microphone with a 1f capacitor. 15 d5 linl left-line input. ac-couple analog audio signal to linl with a 1f capacitor. 16 e6 linr right-line input. ac-couple analog audio signal to linr with a 1f capacitor. 17 d4 jacksns/aux jack sense or auxiliary adc input. when configured for jack detection, jacksns detects the presence or absence of a jack. see the mode configuration section for details. when configured as an auxiliary adc input, aux is used to measure dc voltages. 18 e5 pgnd headphone power ground 19 d3 routp positive right-channel headphone output. connect directly to the load in differential and capacitorless mode. ac-couple to the load in single-ended mode. 20 e4 routn negative right-channel headphone output. inverting output in differential mode. leave unconnected in capacitorless and fast turn-on single-ended mode. bypass with a 1f capacitor to agnd in clickless, single-ended mode. 21 d2 loutn negative left-channel headphone output. noninverting output in differential mode. common headphone return in capacitorless mode. leave unconnected in fast turn-on single-ended mode. bypass with a 1f capacitor to agnd in clickless single-ended mode.
detailed description the MAX9867 is a low-power stereo audio codec designed for portable applications requiring minimum power consumption. the stereo playback path accepts digital audio through a flexible interface compatible with i 2 s, tdm, and left- justified signals. an oversampling sigma-delta dac converts the incoming digital data stream to analog audio and outputs the audio through the stereo head- phone amplifier. the headphone amplifier can be con- figured in differential, single-ended, and capacitorless output modes. the stereo record path has two analog microphone inputs with selectable gain. an integrated microphone bias can be used to power the microphones. the left analog microphone inputs can also accept data from up to two digital microphones. an oversampling sigma- delta adc converts the microphone signals and out- puts the digital bit stream over the digital audio interface. integrated digital filtering provides a range of notch and highpass filters for both the playback and record paths to limit undesirable low-frequency signals and gsm transmission noise. the digital filtering provides attenuation of out-of-band energy by over 70db, eliminating audi- ble aliasing. a digital sidetone function allows audio from the record path to be summed into the playback path after digital filtering. the MAX9867 also includes two stereo, single-ended line inputs with gain adjustment, which can be record- ed by the adcs and/or output by the headphone ampli- fiers. an auxiliary adc accurately measures a dc voltage by utilizing the right audio adc and reporting the dc voltage through the i 2 c interface. a jack detec- tion function allows the detection of headphone, micro- phone, and headset jacks. insertion and removal events can be programmed to trigger a hardware inter- rupt and flag an i 2 c register bit. the MAX9867s flexible clock circuitry utilizes a program- mable clock divider and a digital pll, allowing the dac and adc to operate at maximum dynamic range for all combinations of master clock (mclk) and sample rate (lrclk) without consuming extra supply current. any master clock between 10mhz and 60mhz is supported as are all sample rates from 8khz to 48khz. master and slave modes are supported for maximum flexibility. MAX9867 ultra-low power stereo audio codec ______________________________________________________________________________________ 21 pin description (continued) pin/bump tqfn-ep wlp name function 22 e3 loutp positive left-channel headphone output. connect directly to the load in differential and capacitorless mode. ac-couple to the load in single-ended mode. 23 e2 pvdd headphone power supply. bypass to pgnd with a 1f capacitor. 24, 25 n.c. no connection 26 e1 dvddio digital audio interface power supply. bypass to dgnd with a 1f capacitor. 27 d1 sdout digital audio serial-data adc output 28 c2 sdin digital audio serial-data dac input 29 c1 lrclk digital audio left-right clock input/output. lrclk is the audio sample rate clock and determines whether the audio data on sdin is routed to the left or right channel. in tdm mode, lrclk is a frame synchronization pulse. lrclk is an input when the MAX9867 is in slave mode and an output when in master mode. 30 b1 bclk digital audio bit clock input/output. bclk is an input when the MAX9867 is in slave mode and an output when in master mode. 31 b2 mclk master clock input. acceptable input frequency range: 10mhz to 60mhz. 32 a1 dvdd digital power supply. supply for the digital circuitry and i 2 c interface. bypass to dgnd with a 1f capacitor. ep exposed pad. connect the exposed thermal pad to agnd.
MAX9867 i 2 c registers the MAX9867 audio codec is completely controlled through software using an i 2 c interface. the power-on default setting is complete shutdown, requiring that the internal registers be programmed to activate the device. see table 1 for the devices complete register map. i 2 c slave address the MAX9867 responds to the slave address 0x30 for all write commands and 0x31 for all read operations. ultra-low power stereo audio codec 22 ______________________________________________________________________________________ register b7 b6 b5 b4 b3 b2 b1 b0 register address power- on reset state status status (read only) cld sld ulk 0 0 0 jdet 0 0x00 jack sense (read only) lsns jksns jkmic 0 0 0 0 0 0x01 aux high (read only) aux[15:8] 0x02 aux low (read only) aux[7:0] 0x03 interrupt enable icld isld iulk 0 0 sdodly ijdet 0 0x04 0x00 clock control system clock 0 0 psclk freq 0x05 0x00 stereo audio clock control high pll ni[14:8] 0x06 0x00 stereo audio clock control low ni[7:1] rlk/ ni[0] 0x07 0x00 digital audio interface interface mode mas wci bci dly hizoff tdm 0 0 0x08 0x00 interface mode 0 0 0 lvolfix dmono bsel 0x09 0x00 digital filtering codec filters mode avflt 0 dvflt 0x0a 0x00 level control sidetone dsts 0 dvst 0x0b 0x00 dac level 0 dacm dacg daca 0x0c 0x00 adc level avl avr 0x0d 0x00 left-line input level 0 lilm 0 0 ligl 0x0e 0x00 right-line input level 0 lirm 0 0 ligr 0x0f 0x00 left volume control 0 vollm voll 0x10 0x00 right volume control 0 volrm volr 0x11 0x00 left microphone gain 0 palen pgaml 0x12 0x00 right microphone gain 0 paren pgamr 0x13 0x00 configuration adc input mxinl mxinr auxcap auxgain auxcal auxen 0x14 0x00 microphone micclk digmicl digmicr 0 0 0 0 0x15 0x00 mode dslew vsen zden 0 jdeten hpmode 0x16 0x00 power management system shutdown shdn lnlen lnren 0 dalen daren adlen adren 0x17 0x00 revision rev 0xff 0x42 table 1. i 2 c register map
device status status registers 0x00 and 0x01 are read-only registers that report the status of various device functions. the status register bits are cleared upon reading the status register and are set the next time the event occurs. registers 0x02 and 0x03 report the dc level applied to aux. see the adc section for more details and table 2. MAX9867 ultra-low power stereo audio codec ______________________________________________________________________________________ 23 register b7 b6 b5 b4 b3 b2 b1 b0 register address status (read only) cld sld ulk 0 0 0 jdet 0 0x00 jack s ense ( read o nl y) lsns jksns jkmic 0 0 0 0 0 0x01 aux high (read only) aux[15:8] 0x02 aux low (read only) aux[7:0] 0x03 bits function cld clip detect flag indicates that a signal has reached or exceeded full scale in the adc or dac. sld slew level detect flag when volume or gain changes are made, the slewing circuitry smoothly steps through all intermediate settings. when sld is set high, all slewing has completed and the volume or gain is at its final value. sld is also set when soft-start or stop is complete. ulk digital pll unlock flag indicates that the digital audio pll has become unlocked and digital signal data is not reliable. jdet headset configuration change flag jdet is set whenever there is a change in register 0x01, indicating that the headset configuration has changed. lsns loutp state (valid if shdn = 0, jdeten = 1) lsns is set when the voltage at loutp exceeds avdd - 0.4v. an internal pullup from avdd to loutp causes this condition whenever there is no load on loutp. lsns is only valid in differential and capacitorless output modes. jksns jacksns state (valid if jdeten = 1) jksns is set when the voltage at jacksns exceeds avdd - 0.4v. an internal pullup from avdd to jacksns causes this condition whenever there is no load on jacksns. jkmic microphone detection (valid if palen or paren 00 and jdeten = 1) jkmic is set when jacksns exceeds 0.95 x v micbias . aux auxiliary input measurement aux is a 16-bit signed twos complement number representing the voltage measured at jacksns/aux. before reading a value from aux, set auxcap to 1 to ensure a stable reading. after reading the value, set auxcap to 0. use the following formula to convert the aux value into an equivalent jacksns/aux voltage: k = aux value when auxgain = 1. see the adc section for complete details. table 2. status registers voltage v aux k = ? ? ? ? ? ? 0 738 .
MAX9867 hardware interrupts hardware interrupts are reported on the open-drain irq pin. when an interrupt occurs, irq remains low until the interrupt is serviced by reading the status register 0x00. if a flag is set, it is reported as a hardware interrupt only if the corresponding interrupt enable is set. each bit enables interrupts for the status flag in the respective bit location in register 0x00. see table 3. sdodly is used to control the sdout timing. see the digital audio interface section for a detailed description. clock control the MAX9867 can work with a master clock (mclk) supplied from any system clock within the 10mhz-to- 60mhz range. internally, the MAX9867 requires a 10mhz-to-20mhz clock. a prescaler divides mclk by 1, 2, or 4 to create the internal clock (pclk). pclk is used to clock all portions of the MAX9867. see table 4. the MAX9867 is capable of supporting any sample rate from 8khz to 48khz, including all common sample rates (8khz, 16khz, 24khz, 32khz, 44.1khz, and 48khz). to accommodate a wide range of system architectures, the MAX9867 supports three main clocking modes: ? normal: this mode uses a 15-bit clock divider coeffi- cient to set the sample rate relative to the prescaled mclk input (pclk). this allows high flexibility in both the mclk and lrclk frequencies and can be used in either master or slave mode. ? exact integer: in both master and slave mode, com- mon mclk frequencies (12mhz, 13mhz, 16mhz, and 19.2mhz) can be programmed to operate in exact integer mode for both 8khz and 16khz sample rates. in these modes, the mclk and lrclk rates are selected by using the freq bits instead of the ni and pll control bits. ? pll: when operating in slave mode, a pll can be enabled to lock onto externally generated lrclk signals that are not integer related to pclk. prior to enabling the interface, program ni to the nearest desired ratio and set the ni[0] = 1 to enable the plls rapid lock mode. if ni[0] = 0, then ni is ignored and pll lock time is slower. ultra-low power stereo audio codec 24 ______________________________________________________________________________________ register b7 b6 b5 b4 b3 b2 b1 b0 register address interrupt enable icld isld iulk 0 0 sdodly ijdet 0 0x04 table 3. interrupt registers register b7 b6 b5 b4 b3 b2 b1 b0 register system clock 0 0 psclk freq 0x05 stereo audio clock control high pll ni[14:8] 0x06 stereo audio clock control low ni[7:1] ni[0] 0x07 table 4. clock control registers bits function psclk mclk prescaler divides mclk to generate a pclk between 10mhz and 20mhz. 00 = disable clock for low-power shutdown. 01 = select if mclk is between 10mhz and 20mhz. 10 = select if mclk is between 20mhz and 40mhz. 11 = select if mclk is between 40mhz and 60mhz.
MAX9867 ultra-low power stereo audio codec ______________________________________________________________________________________ 25 bits function exact integer modes allows integer sampling for specific pclk (prescaled mclk) frequencies and 8khz or 16khz sample rates. freq[3:0] pclk (mhz) lrclk (khz) pclk/lrclk 0x00 normal or pll mode 0x1?x7 reserved reserved reserved 0x8 0x9 12 12 8 16 1500 750 0xa 0xb 13 13 8 16 1625 812.5 0xc 0xd 16 16 8 16 2000 1000 0xe 0xf 19.2 19.2 8 16 2400 1200 freq modes 0x8C0xf are available in either master or slave mode. in slave mode, if the indicated pclk/lrclk ratio cannot be guaranteed, use pll mode instead. pll pll mode enable 0 = valid for slave and master mode. the frequency of lrclk is set by the ni divider bits. in master mode, the MAX9867 generates lrclk using the specified divide ratio. in slave mode, the MAX9867 expects an lrclk as specified by the divide ratio. 1 = valid for slave mode only. a digital pll locks on to any externally supplied lrclk signal. rapid lock mode to enable rapid lock mode, set ni to the nearest desired ratio and set ni[0] = 1 before enabling the interface. ni normal mode lrclk divider when pll = 0, the frequency of lrclk is determined by ni. see table 5 for common ni values. ni = (65536 x 96 x f lrclk )/f pclk f lrclk = lrclk frequency f pclk = prescaled mclk internal clock frequency (pclk) lrclk > 24khz is only valid for mode = 0 (stereo audio mode). mode = 1 (voice mode) requires lrclk 24khz. table 4. clock control registers (continued) lrclk (khz) mclk (mhz) psclk 8 16 24 32 44.1 48 11.2896 01 0x116a 0x22d4 0x343f 0x45a9 0x6000 0x687d 12 01 0x1062 0x20c5 0x3127 0x4189 0x5a51 0x624e 12.288 01 0x1000 0x2000 0x3000 0x4000 0x5833 0x6000 13 01 0x0f20 0x1e3f 0x2d5f 0x3c7f 0x535f 0x5abe 19.2 01 0x0a3d 0x147b 0x1eb8 0x28f6 0x3873 0x3d71 24 10 0x1062 0x20c5 0x1893 0x4189 0x5a51 0x624e 26 10 0x0f20 0x1e3f 0x16af 0x3c7f 0x535f 0x5abe 27 10 0x0e90 0x1d21 0x15d8 0x3a41 0x5048 0x5762 note: bolded values are exact integers that provide maximum full-scale performance. table 5. common ni values
MAX9867 ultra-low power stereo audio codec 26 ______________________________________________________________________________________ register b7 b6 b5 b4 b3 b2 b1 b0 register address interface mode mas wci bci dly hizoff tdm 0 0 0x08 interface mode 0 0 0 lvolfix dmono bsel 0x09 bits function mas master mode 0 = the MAX9867 operates in slave mode with lrclk and bclk configured as inputs. 1 = the MAX9867 operates in master mode with lrclk and bclk configured as outputs. wci lrclk invert 0 = left-channel data is input and output while lrclk is low. 1 = right-channel data is input and output while lrclk is low. note: wci is ignored when tdm = 1. bci bclk invert in master and slave modes: 0 = sdin is latched into the part on the rising edge of bclk. sdout transitions after the rising edge of bclk as determined by sdodly . 1 = sdin is latched into the part on the falling edge of bclk. sdout transitions after the falling edge of bclk as determined by sdodly . in master mode: 0 = lrclk changes state immediately after the rising edge of bclk. 1 = lrclk changes state immediately after the falling edge of bclk. sdodly sdout delay 0 = sdout transitions one half bclk cycle after sdin is latched into the part. 1 = sdout transitions on the same bclk edge as sdin is latched into the part. see figures 1C4 for complete details. see register 0x04 (interrupt registers). dly delay mode 0 = sdin/sdout data is latched on the first bclk edge following an lrclk edge. 1 = sdin/sdout data is assumed to be delayed one bclk cycle so that it is latched on the 2nd bclk edge following an lrclk edge (i 2 s-compatible mode). note: dly is ignored when tdm = 1. hizoff sdout high-impedance mode 0 = sdout goes to a high-impedance state after all data bits have been transferred out of the MAX9867, allowing sdout to be shared by other devices. 1 = sdout is set either high or low after all data bits have been transferred out of the MAX9867. note: high-impedance mode is intended for use when tdm = 1. lvolfix see the line inputs section. table 6. digital audio interface registers digital audio interface the MAX9867s digital audio interface supports a wide range of operating modes to ensure maximum compati- bility. see figures 1C4 for timing diagrams. in master mode, the MAX9867 outputs lrclk and bclk, while in slave mode they are inputs. when operating in master mode, bclk can be configured in a number of ways to ensure compatiblity with other audio devices. lvolfix is used to fix the line input playback volume to 0db regardless of voll and volr. see the line inputs section for complete details and table 6.
MAX9867 ultra-low power stereo audio codec ______________________________________________________________________________________ 27 bits function tdm tdm mode select 0 = lrclk signal polarity indicates left and right audio. 1 = lrclk is a framing pulse that transitions polarity to indicate the start of a frame of audio data consisting of multiple channels. when operating in tdm mode, the left channel is output immediately following the frame sync pulse. if right- channel data is being transmitted, the 2nd channel of data immediately follows the 1st channel data. dmono mono playback mode 0 = stereo data input on sdin is processed separately. 1 = stereo data input on sdin is mixed to a single channel and routed to both the left and right dac. bsel bclk select configures bclk when operating in master mode. bsel has no effect in slave mode. set bsel = 010, unless sharing the bus with multiple devices: 000 = off 001 = 64x lrclk (192x internal clock divided by 3) 010 = 48x lrclk (192x internal clock divided by 4) 011 = reserved for future use. 100 = pclk/2 101 = pclk/4 110 = pclk/8 111 = pclk/16 table 6. digital audio interface registers (continued)
audio master modes: left justified: wci = 0, bci = 0, dly = 0, sdodly = 0 left justified + lrclk invert: wci = 1, bci = 0, dly = 0, sdodly = 0 left justified + bclk invert: wci = 0, bci = 1, dly = 0, sdodly = 0 lrclk bclk sdout sdin d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1/f s 1/f s configured by bsel 7ns (typ) 7ns (typ) d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 25ns (min) 7ns (typ) 7ns (typ) 0ns (min) 40ns (max) 0ns (min) configured by bsel 7ns (typ) 25ns (min) 7ns (typ) 0ns (min) configured by bsel 25ns (min) 0ns (min) 40ns (max) 0ns (min) relative to pclk (see note) right lrclk bclk sdout sdin 7ns (typ) 7ns (typ) relative to pclk (see note) lrclk bclk sdout sdin d15 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d15 7ns (typ) 7ns (typ) 40ns (max) 0ns (min) relative to pclk (see note) d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d15 note: the delay from a bclk edge and an lrclk edge is determined by length of time that pclk (the internally divided down version of mclk as defined by the psclk bits) is high during one period of mclk plus the internal delay. for example: if pclk = 12.288mhz, then the delay between bclk and lrclk is typicall y 45ns. left 1/f s 7ns (typ) 7ns (typ) right left right left figure 1. digital audio interface audio master mode example (sheet 1 of 2) MAX9867 ultra-low power stereo audio codec 28 ______________________________________________________________________________________
MAX9867 ultra-low power stereo audio codec ______________________________________________________________________________________ 29 i 2 s: wci = 0, bci = 0, dly = 1, sdodly = 0 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 configured by bsel 7ns (typ) 25ns (min) 7ns (typ) 0ns (min) configured by bsel 7ns (typ) 25ns (min) 7ns (typ) 0ns (min) 40ns (max) 0ns (min) d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 40ns (max) 0ns (min) d15 d15 lrclk bclk sdout sdin note: the delay from a bclk edge and an lrclk edge is determined by length of time that pclk (the internally divided down version of mclk as defined by the psclk bits) is high during one period of mclk plus the internal delay. for example: if pclk = 12.288mhz, then the delay between bclk and lrclk is typicall y 45ns. left justified: wci = 0, bci = 0, dly = 0, sdodly = 1 lrclk bclk sdout sdin relative to pclk (see note) 1/f s 7ns (typ) 7ns (typ) right left relative to pclk (see note) 1/f s 7ns (typ) 7ns (typ) right left figure 1. digital audio interface audio master mode example (sheet 2 of 2)
MAX9867 ultra-low power stereo audio codec 30 ______________________________________________________________________________________ voice (tdm, pcm) master modes: bci = 0, hizoff = 0, sdodly = 0 lrclk bclk sdout sdin l14 l13 l12 l11 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 configured by bsel 25ns (min) 0ns (min) 40ns (max) 0ns (min) l15 relative to pclk (see note) bci = 1, hizoff = 0, sdodly = 0 bci = 0, hizoff = 1, sdodly = 0 lrclk bclk sdout lrclk bclk sdout sdin r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 r15 l14 l13 l12 l11 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 l15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 r15 lrclk bclk sdout sdin bci = 0, hizoff = 0, sdodly = 1 7ns (typ) 7ns (typ) 7ns (typ) 7ns (typ) configured by bsel 25ns (min) 0ns (min) l14 l13 l12 l11 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 l15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 r15 7ns (typ) 7ns (typ) configured by bsel 25ns (min) 0ns (min) l14 l13 l12 l11 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 l15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 r15 sdin configured by bsel 25ns (min) 0ns (min) l14 l13 l12 l11 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 l15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 r15 1/f s l14 l13 l12 l11 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 40ns (max) 0ns (min) l15 relative to pclk (see note) r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 r15 7ns (typ) 7ns (typ) 7ns (typ) 7ns (typ) l14 l13 l12 l11 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 40ns (max) 0ns (min) l15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 r15 1/f s relative to pclk (see note) 7ns (typ) 7ns (typ) 1/f s l14 l13 l12 l11 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 40ns (max) 0ns (min) l15 relative to pclk (see note) r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 r15 7ns (typ) 7ns (typ) 7ns (typ) 7ns (typ) 1/f s figure 2. digital audio interface voice master mode examples
MAX9867 ultra-low power stereo audio codec ______________________________________________________________________________________ 31 audio slave modes: left justified: wci = 0, bci = 0, dly = 0, sdodly = 0 left justified + lrclk invert: wci = 1, bci = 0, dly = 0, sdodly = 0 left justified + bclk invert: wci = 0, bci = 1, dly = 0, sdodly = 0 lrclk bclk sdout sdin d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1/f s 1/f s 30ns (min) 30ns (min) 75ns (min) 30ns (min) 75ns (min) 30ns (min) 75ns (min) 0ns (min) 0ns (min) 0ns (min) d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 25ns (min) 25ns (min) 0ns (min) 40ns (max) 0ns (min) 30ns (min) 30ns (min) 25ns (min) 25ns (min) 40ns (max) 0ns (min) 25ns (min) 0ns (min) 25ns (min) 0ns (min) right lrclk bclk sdout sdin lrclk bclk sdout sdin d15 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d15 40ns (max) 0ns (min) d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d15 left 1/f s right left right left figure 3. digital audio interface audio slave mode examples (sheet 1 of 2)
MAX9867 ultra-low power stereo audio codec 32 ______________________________________________________________________________________ i 2 s: wci = 0, bci = 0, dly = 1, sdodly = 0 0ns (min) 0ns (min) d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 30ns (min) 75ns (min) 30ns (min) 30ns (min) 75ns (min) 30ns (min) 25ns (min) 25ns (min) 25ns (min) 0ns (min) 25ns (min) 0ns (min) 40ns (max) 0ns (min) d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 40ns (max) 0ns (min) d15 d15 lrclk bclk sdout sdin left justified: wci = 0, bci = 0, dly = 0, sdodly = 1 lrclk bclk sdout sdin 1/f s right left 1/f s right left figure 3. digital audio interface audio slave mode examples (sheet 2 of 2)
MAX9867 ultra-low power stereo audio codec ______________________________________________________________________________________ 33 voice (tdm, pcm) slave modes: bci = 0, hizoff = 0, sdodly = 0 lrclk bclk sdout sdin l14 l13 l12 l11 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 75ns (min) 25ns (min) 0ns (min) 40ns (max) 0ns (min) l15 25ns (min) bci = 1, hizoff = 0, sdodly = 0 bci = 0, hizoff = 1, sdodly = 0 lrclk bclk sdout lrclk bclk sdout sdin r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 r15 l14 l13 l12 l11 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 l15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 r15 lrclk bclk sdout sdin bci = 0, hizoff = 0, sdodly = 1 30ns (min) 30ns (min) 75ns (min) 30ns (min) 30ns (min) 40ns (max) 0ns (min) 25ns (min) 40ns (max) 0ns (min) 25ns (min) 40ns (max) 0ns (min) 25ns (min) 25ns (min) 0ns (min) l14 l13 l12 l11 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 l15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 r15 25ns (min) 0ns (min) l14 l13 l12 l11 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 l15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 r15 sdin 25ns (min) 0ns (min) l14 l13 l12 l11 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 l15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 r15 1/f s l14 l13 l12 l11 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 l15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 r15 l14 l13 l12 l11 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 l15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 r15 1/f s 1/f s l14 l13 l12 l11 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 l15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 r15 1/f s 75ns (min) 30ns (min) 30ns (min) 75ns (min) 30ns (min) 30ns (min) 0ns (min) 0ns (min) 0ns (min) 0ns (min) 0ns (min) 0ns (min) 0ns (min) 0ns (min) figure 4. digital audio interface voice slave mode examples
MAX9867 ultra-low power stereo audio codec 34 ______________________________________________________________________________________ digital filtering the MAX9867 incorporates both iir (voice) and fir (audio) digital filters to accomodate a wide range of audio sources. the iir fiilters provide over 70db of stopband attenuation as well as selectable highpass fil- ters. the fir filters provide low-power consumption and are linear phase to maintain stereo imaging. table 7 is the digital filtering register. register b7 b6 b5 b4 b3 b2 b1 b0 register address codec filters mode avflt 0 dvflt 0x0a bits function mode digital audio filter mode 0 = iir voice filters 1 = fir audio filters avflt adc digital audio filter mode = 0 select the desired digital filter response from table 8. see the frequency response graph in the typical operating characteristics section for details on each filter. mode = 1 0x0 = dc-blocking filter is disabled. any other setting = dc-blocking filter is enabled. dvflt dac digital audio filter mode = 0 select the desired digital filter response from table 8. see the frequency response graph in the typical operating characteristics section for details on each filter. mode = 1 0x0 = dc-blocking filter is disabled. any other setting = dc-blocking filter is enabled. table 7. digital filtering register code filter type intended sample rate (khz) highpass corner frequency (hz) 217hz notch 0x0 disabled 0x1 elliptical 16 256 yes 0x2 butterworth 16 500 no 0x3 elliptical 8 256 yes 0x4 butterworth 8 500 no 0x5 butterworth 8 to 24 f s /240 no 0x6 to 0x7 reserved table 8. iir highpass digital filters
MAX9867 ultra-low power stereo audio codec ______________________________________________________________________________________ 35 digital gain control the MAX9867 includes digital gain adjustment for the playback and record paths. independent gain adjust- ment is provided for the two record channels. sidetone gain adjustment is also provided to set the sidetone level relative to the playback level. table 9 is the digital gain registers. register b7 b6 b5 b4 b3 b2 b1 b0 register address sidetone dsts 0 dvst 0x0b dac level 0 dacm dacg daca 0x0c adc level avl avr 0x0d bits function dsts digital sidetone source mixer 00 = no sidetone is selected. 01 = left adc 10 = right adc 11 = left + right adc digital sidetone level control all gain settings are relative to the adc input voltage. differential headphone output mode setting gain (db) setting gain (db) setting gain (db) 0x00 off 0x0b -20 0x16 -42 0x01 0 0x0c -22 0x17 -44 0x02 -2 0x0d -24 0x18 -46 0x03 -4 0x0e -26 0x19 -48 0x04 -6 0x0f -28 0x1a -50 0x05 -8 0x10 -30 0x1b -52 0x06 -10 0x11 -32 0x1c -54 0x07 -12 0x12 -34 0x1d -56 0x08 -14 0x13 -36 0x1e -58 0x09 -16 0x14 -38 0x1f -60 0x0a -18 0x15 -40 capacitorless and single-ended headphone output mode setting gain (db) setting gain (db) setting gain (db) 0x00 off 0x0b -25 0x16 -47 0x01 -5 0x0c -27 0x17 -49 0x02 -7 0x0d -29 0x18 -51 0x03 -9 0x0e -31 0x19 -53 0x04 -11 0x0f -33 0x1a -55 0x05 -13 0x10 -35 0x1b -57 0x06 -15 0x11 -37 0x1c -59 0x07 -17 0x12 -39 0x1d -61 0x08 -19 0x13 -41 0x1e -63 0x09 -21 0x14 -43 0x1f -65 dvst 0x0a -23 0x15 -45 dacm dac mute enable 0 = no mute 1 = mute table 9. digital gain registers
MAX9867 ultra-low power stereo audio codec 36 ______________________________________________________________________________________ bits function dacg dac gain 00 = 0db 01 = +6db 10 = +12db 11 = +18db note: dacg is only used when mode = 0. if mode = 1, the dac level is only set by daca. dac level control daca works in all modes. setting gain (db) setting gain (db) 0x0 0 0x8 -8 0x1 -1 0x9 -9 0x2 -2 0xa -10 0x3 -3 0xb -11 0x4 -4 0xc -12 0x5 -5 0xd -13 0x6 -6 0xe -14 daca 0x7 -7 0xf -15 adc left/right level control setting gain (db) setting gain (db) 0x0 +3 0x8 -5 0x1 +2 0x9 -6 0x2 +1 0xa -7 0x3 0 0xb -8 0x4 -1 0xc -9 0x5 -2 0xd -10 0x6 -3 0xe -11 avl/avr 0x7 -4 0xf -12 table 9. digital gain registers (continued) line inputs the MAX9867 includes one pair of single-ended line inputs. when enabled, the line inputs connect directly to the headphone amplifier and can be optionally con- nected to the adc for recording. table 10 lists the line input registers. table 10. line input registers register b7 b6 b5 b4 b3 b2 b1 b0 register address left-line input level 0 lilm 0 0 ligl 0x0e right-line input level 0 lirm 0 0 ligr 0x0f
MAX9867 ultra-low power stereo audio codec ______________________________________________________________________________________ 37 bits function lilm/lirm line-input left/right playback mute 0 = line input is connected to the headphone amplifiers. 1 = line input is disconnected from the headphone amplifiers. line-input left/right gain setting gain (db) setting gain (db) 0x0 +24 0x8 +8 0x1 +22 0x9 +6 0x2 +20 0xa +4 0x3 +18 0xb +2 0x4 +16 0xc 0 0x5 +14 0xd -2 0x6 +12 0xe -4 ligl/ligr 0x7 +10 0xf -6 lvolfix fix line input volume 0 = line input to headphone output volume tracks voll and volr bits. 1 = line input to headphone output volume fixed at voll and volr bits. see the digital audio interface section. table 10. line input registers (continued) playback volume the MAX9867 incorporates volume and mute control to allow level control for the playback audio path. program registers 0x10 and 0x11 to set the desired volume. see table 11. table 11. playback volume registers register b7 b6 b5 b4 b3 b2 b1 b0 register address left volume control 0 vollm voll 0x10 right volume control 0 volrm volr 0x11
MAX9867 ultra-low power stereo audio codec 38 ______________________________________________________________________________________ table 11. playback volume registers (continued) microphone inputs two differential microphone inputs and a low-noise micro- phone bias for powering the microphones are provided by the MAX9867. in typical applications, the left micro- phone records a voice signal and the right microphone records a background noise signal. in applications that require only one microphone, use the left microphone input and disable the right adc. the microphone signals are amplified by two stages of gain and then routed to the adcs. the first stage offers selectable 0db, 20db, or 30db settings. the second stage is a programmable gain amplifier (pga) adjustable from 0db to 20db in 1db steps. zero-crossing detection is included on the pga to minimize zipper noise while making gain changes. see figure 5 for a detailed diagram of the microphone input structure. table 12 is the microphone input register. table 12. microphone input register register b7 b6 b5 b4 b3 b2 b1 b0 register address left microphone gain 0 palen pgaml 0x12 right microphone gain 0 paren pgamr 0x13 bits function vollm/volrm left/right playback mute vollm and volrm mute both the dac and line input audio signals. 0 = audio playback is unmuted. 1 = audio playback is muted note: vsen has no effect on the mute function. when vollm or volrm is set, the output is muted immediately ( zden = 1) or at the next zero-crossing ( zden = 0). left/right playback volume voll and volr control the playback volume for both the dac and line input audio signals. setting gain (db) setting gain (db) setting gain (db) 0x00 +6 0x0e -5 0x1c -42 0x01 +5.5 0x0f -6 0x1d -46 0x02 +5 0x10 -8 0x1e -50 0x03 +4.5 0x11 -10 0x1f -54 0x04 +4 0x12 -12 0x20 -58 0x05 +3.5 0x13 -14 0x21 -62 0x06 +3 0x14 -16 0x22 -66 0x07 +2 0x15 -18 0x23 -70 0x08 +1 0x16 -20 0x24 -74 0x09 0 0x17 -22 0x25 -78 0x0a -1 0x18 -26 0x26 -82 0x0b -2 0x19 -30 0x27 -84 0x0c -3 0x1a -34 0x0d -4 0x1b -38 0x28 to 0x3f mute voll/volr note: gain settings apply when the headphone amplifier is configured in differential mode. in the single- ended and capacitorless modes, the actual gain is 5db lower for each setting.
MAX9867 ultra-low power stereo audio codec ______________________________________________________________________________________ 39 bits function palen/paren left/right microphone preamplifier gain enables the microphone circuitry and sets the preamplifier gain. 00 = disabled 01 = 0db 10 = +20db 11 = +30db left/right microphone programmable gain amplifier setting gain (db) setting gain (db) 0x00 +20 0x0b +9 0x01 +19 0x0c +8 0x02 +18 0x0d +7 0x03 +17 0x0e +6 0x04 +16 0x0f +5 0x05 +15 0x10 +4 0x06 +14 0x11 +3 0x07 +13 0x12 +2 0x08 +12 0x13 +1 0x09 +10 pgaml/pgamr 0x0a +11 0x14 to 0x1f 0 micln miclp micbias pga pga - preamp micrn adc l micrp 1.5v 0/20/30db 0db to +20db 0db to +20db v reg v reg 0/20/30db preamp MAX9867 adc r figure 5. microphone input signal path table 12. microphone input register (continued)
MAX9867 ultra-low power stereo audio codec 40 ______________________________________________________________________________________ adc the MAX9867 includes two 16-bit adcs. the first adc is used to record left-channel microphone and line-input audio signals. the second adc can be used to record right-channel microphone and line-input signals, or it can be configured to accurately measure dc voltages. when measuring dc voltages, both the left and right adcs must be enabled by setting adlen and adren in register 0x17. the input to the second adc is jack- sns/aux and the output is reported in aux (registers 0x02 and 0x03). since the audio adc is used to per- form the measurement, the digital audio interface must be properly configured. if the left adc is being used to convert audio, the dc measurement is performed at the same sample rate. when not using the left adc, config- ure the digital interface for a 48khz sample rate to ensure the fastest possible settling time. to ensure accurate results, the MAX9867 includes two calibration routines. calibrate the adc each time the MAX9867 is powered on. calibration settings are not lost if the MAX9867 is placed in shutdown. when mak- ing a measurement, set auxcap to 1 to prevent aux from changing while reading the registers. setup procedure 1) ensure a valid mclk signal is provided and config- ure psclk appropriately. 2) choose a clocking mode. the following options are possible: ? slave mode with lrclk and bclk signals pro- vided. the measurement sample rate is deter- mined by the external clocks. ? slave mode with no lrclk and bclk signals provided. configure the device for normal clock mode using the ni ratio. select f s = 48khz to allow for the fastest settling times. ? master mode with audio. configure the device in normal mode using the ni ratio or exact integer mode using freq as required by the audio signal. ? master mode without audio. configure the device in normal mode using the ni ratio. select f s = 48khz to allow for the fastest settling times. 3) ensure jacksns is disabled. 4) enable the left and right adc; take the MAX9867 out of shutdown. offset calibration procedure perform the following steps before the first dc mea- surement is taken after applying power to the MAX9867: 1) enable the aux input (auxen = 1). 2) enable the offset calibration (auxcal = 1). 3) wait the appropriate time (see table 13). 4) complete calibration (auxcal = 0). gain calibration procedure perform the following steps the first time a dc measure- ment is taken after applying power to the MAX9867 or if the temperature changes significantly: 1) enable the aux input (auxen = 1). 2) start gain calibration (auxgain = 1). 3) wait the appropriate time (see table 13). 4) freeze the measurement results (auxcap = 1). 5) read aux and store the value in memory to correct all future measurements (k = (aux[15:0], k is typi- cally 19500). 6) complete calibration (auxgain = auxcap = 0). dc measurement procedure perform the following steps after offset and gain cali- bration are complete: 1) enable the aux input (auxen = 1). 2) wait the appropriate time (see table 13). 3) freeze the measurement results (auxcap = 1). 4) read aux and correct with the gain calibration value: 5) complete measurement (auxcap = 0). v aux k aux = ? ? ? ? ? ? 0 738 15 0 . [:] table 13. aux adc wait times wait times lrclk (khz) wait time (ms) 48 40 44.1 44 32 60 24 80 22.05 90 16 120 12 160 11.025 175 8 240
MAX9867 ultra-low power stereo audio codec ______________________________________________________________________________________ 41 complete dc measurement example mclk = 13mhz, slave mode, bclk and lrclk not externally supplied: 1) configure the digital audio interface for f s = 48khz (psclk = 01, freq = 0x0, pll = 0, ni = 0x5abe, mas = 0). 2) disable jacksns (jdeten = 0). 3) enable the left and right adc; take the MAX9867 out of shutdown (adlen = adren = shdn = 1). 4) calibrate the offset: a. enable the aux input (auxen = 1). b. enable the offset calibration (auxcal = 1). c. wait 40ms. d. complete calibration (auxcal = 0). 5) calibrate the gain: a. start gain calibration (auxgain = 1). b. wait 40ms. c. freeze the measurement results (auxcap = 1). d. read aux and store the value in memory to cor- rect all future measurements (k = (aux[15:0]). e. complete calibration (auxgain = auxcap = auxen = 0). 6) measure the voltage on jacksns/aux: a. enable the aux input (auxen = 1). b. wait 40ms. c. freeze the measurement results (auxcap = 1). d. read aux and correct with the gain calibration value. e. complete measurement (auxcap = 0). 7) dc measurement complete. table 14. adc input register register b7 b6 b5 b4 b3 b2 b1 b0 register address adc input mxinl mxinr auxcap au x gain auxcal auxen 0x14 bits function mxinl/mxinr left/right adc audio input mixer 00 = no input is selected. 01 = left/right analog microphone 10 = left/right line input 11 = left/right analog microphone + line input note: if the right-line input is disabled, then the left-line input is connected to both mixers. enabling the left and right digital microphones disables the left and right audio mixers, respectively. see digmicl/ digmicr in table 15 for more details. auxcap auxiliary input capture 0 = update aux with the voltage at jacksns/aux. 1 = hold aux for reading. auxgain auxiliary input gain calibration 0 = normal operation 1 = the input buffer is disconnected from jacksns/aux and connected to an internal voltage reference. while in this mode, read the aux register and store the value. use the stored value as a gain calibration factor, k, on subsequent readings. auxcal auxiliary input offset calibration 0 = normal operation 1 = jacksns/aux is disconnected from the input and the adc automatically calibrates out any internal offsets. auxen auxiliary input enable 0 = use jacksns/aux for jack detection. 1 = use jacksns/aux for dc measurements. note: for auxen = 1, set mxinr = 00, adlen = 1, and adren = 1.
MAX9867 ultra-low power stereo audio codec 42 ______________________________________________________________________________________ digital microphone input the MAX9867 can accept audio from up to two digital microphones. when using digital microphones, the left analog microphone input is retasked as a digital micro- phone input. the right analog microphone input is still available to allow a combination of analog and digital microphones to be used. figure 6 shows the digital microphone interface timing diagram. see table 15. table 15. digital microphone input register register b7 b6 b5 b4 b3 b2 b1 b0 register address microphone micclk digmicl digmicr 0 0 0 0 0x15 bits function micclk digital microphone clock 00 = pclk/8 01 = pclk/6 10 = reserved 11 = reserved digital left/right microphone enable digmicl digmicr left adc input right adc input 0 0 adc input mixer adc input mixer 01 line input (left analog microphone unavailable) right digital microphone 1 0 left digital microphone adc input mixer 1 1 left digital microphone right digital microphone digmicl/digmicr note: the left analog microphone input is never available when digmicl or digmicr = 1. digmicclk digmicdata t su, mic t hd, mic t su, mic t hd, mic left right left right 1/f micclk figure 6. digital microphone timing diagram
MAX9867 ultra-low power stereo audio codec ______________________________________________________________________________________ 43 mode configuration the MAX9867 includes circuitry to minimize click-and- pop during volume changes, detect headsets, and con- figure the headphone amplifier mode. both volume slewing and zero-crossing detection are included to ensure click-and-pop free volume transitions. table 16 is the mode configuration register. headset detection overview the MAX9867 features headset detection that can detect the insertion and removal of a jack as well as the load type. when a jack is detected, an interrupt on irq can be triggered to alert the microcontroller of the event. figure 7 shows the typical configuration for jack detection. sleep-mode headset detection when the MAX9867 is in shutdown and the power supply is available, sleep-mode headset detection can be enabled to detect jack insertion. sleep mode applies a 4a pullup current to jacksns/aux and loutp that forces the voltage on jacksns/aux and loutp to avdd when no load is applied. when a jack is inserted, either jacksns, loutp (assuming the headphone amplifier is not configured in single-ended mode), or both are loaded sufficiently to reduce the output voltage to nearly 0v and clear the jksns or lsns bits, respectively. the change in the lsns and jksns bits sets jdet and triggers an interrupt on irq if ijdet is set. the interrupt signals the microcontroller that a jack has been inserted, allowing the microcontroller to respond as desired. powered-on headset detection when the MAX9867 is in normal operation and the micro- phone interface is enabled, jack insertion and removal can be detected through the jacksns/aux pin. as shown in figure 7, v mic is pulled up by micbias. when a micro- phone is connected, v mic is assumed to be between 0v and 95% of v micbias . if the jack is removed, v mic increas- es to v micbias . this event causes jkmic to be set, alert- ing the system that the headset has been removed. alternatively, if the jack is inserted, v mic decreases to below 95% of v micbias and jkmic is cleared, alerting the system that a jack has been inserted. the jkmic bit can be configured to create a hardware interrupt that alerts the microcontroller of jack removal and insertion events. headphone modes the headphone amplifier supports differential, single- ended, and capacitorless output modes, as shown in figure 8. in each mode, the amplifier can be configured for stereo or mono operation. the differential and capacitorless modes are inherently click and pop free. the single-ended mode optionally includes click-and- pop reduction to eliminate the click and pop that would normally be caused by the output coupling capacitor. when click-and-pop reduction is not required in the sin- gle-ended configuration, leave loutn and routn unconnected. gnd mic hpr hpl loutp routp micbias jacksns/aux miclp loutn figure 7. typical configuration for headset detection loutp loutn routp routn differential loutp loutn routp routn capacitorless 1 f loutp 220 f loutn single ended 1 f routp 220 f routn optional components required for click and pop suppression only figure 8. headphone amplifier modes
MAX9867 ultra-low power stereo audio codec 44 ______________________________________________________________________________________ table 16. mode configuration register register b7 b6 b5 b4 b3 b2 b1 b0 register address mode dslew vsen zden 0 jdeten hpmode 0x16 bits function dslew digital volume slew speed 0 = digital volume changes are slewed over 10ms. 1 = digital volume changes are slewed over 80ms. vsen volume change smoothing 0 = volume changes slew through all intermediate values. 1 = volume changes occur in one step. zden line input zero-crossing detection 0 = line input volume changes occur at zero crossings in the audio waveform or after 62ms if no zero crossing occurs. 1 = line-input volume changes occur immediately. jdeten jack detection enable shdn = 0: sleep mode enables pullups on loutp and jacksns/aux to detect jack insertion. lsns and jksns are valid. loutp detection is only valid in differential and capacitorless output modes. shdn = 1: normal mode enables the comparator circuitry on jacksns/aux to detect voltage changes. jkmic is valid if the microphone circuitry is enabled. note: auxen must be set to 0 for jack detection to function. headphone amplifier mode hpmode mode 000 stereo differential (clickless) 001 mono (left) differential (clickless) 010 stereo capacitorless (clickless) 011 mono (left) capacitorless (clickless) 100 stereo single-ended (clickless) 101 mono (left) single-ended (clickless) 110 stereo single-ended (fast turn-on) 111 mono (left) single-ended (fast turn-on) hpmode note: in mono operation, the right amplifier is disabled.
MAX9867 ultra-low power stereo audio codec ______________________________________________________________________________________ 45 power management the MAX9867 includes complete power management control to minimize power usage. the dac and both adc can be independently enabled so that only the required circuitry is active. toggle the shdn bit when- ever a configuration change is made. table 17 is the power-management register. table 17. power-management register register b7 b6 b5 b4 b3 b2 b1 b0 register address system shutdown shdn lnlen lnren 0 dalen daren adlen adren 0x17 bits function shdn shutdown places the device in low-power shutdown mode. lnlen left-line input enable enables the left-line input preamp and automatically enables the left and right headphone amplifiers. if lnren = 0, the left-line input signal is also routed to the right adc input mixer and right headphone amplifier. note: control of the right headphone amplifier can be overridden by hpmode. lnren right-line input enable enables the right-line input preamp and automatically enables the right headphone amplifier. note: control of the right headphone amplifier can be overridden by hpmode. dalen left dac enable e nab l es the l eft d ac and autom ati cal l y enab l es the l eft and r i g ht head p hone am p l i fi er s. if d are n = 0, the l eft d ac si g nal i s al so r outed to the r i g ht head p hone am p l i fi er . note: control of the right headphone amplifier can be overridden by hpmode. daren right dac enable enabling the right dac must be done in the same i 2 c write operation that enables the left dac. right dac operation requires dalen = 1. adlen left adc enable adren right adc enable enabling the right adc must be done in the same i 2 c write operation that enables the left adc. the right adc can be enabled while the left adc is running if used for dc measurements. shdn must be toggled to disable the right adc in this case. right adc operation requires adlen = 1. revision code the MAX9867 includes a revision code to allow easy identification of the device revision. the revision code is 0x42. see table 18 for the revision code register. table 18. revision code register register b7 b6 b5 b4 b3 b2 b1 b0 register address revision rev 0xff
MAX9867 ultra-low power stereo audio codec 46 ______________________________________________________________________________________ i 2 c serial interface the MAX9867 features an i 2 c/smbus-compatible, 2-wire serial interface consisting of a serial-data line (sda) and a serial-clock line (scl). sda and scl facili- tate communication between the MAX9867 and the mas- ter at clock rates up to 400khz. figure 9 shows the 2-wire interface timing diagram. the master generates scl and initiates data transfer on the bus. the master device writes data to the MAX9867 by transmitting the proper slave address followed by the register address and then the data word. each transmit sequence is framed by a start (s) or repeated start (sr) condi- tion and a stop (p) condition. each word transmitted to the MAX9867 is 8 bits long and is followed by an acknowledge clock pulse. a master reading data from the MAX9867 transmits the proper slave address followed by a series of nine scl pulses. the MAX9867 transmits data on sda in sync with the master-generated scl pulses. the master acknowledges receipt of each byte of data. each read sequence is framed by a start or repeated start condition, a not acknowledge, and a stop condition. sda operates as both an input and an open-drain output. a pullup resistor, typically greater than 500 is required on sda. scl operates only as an input. a pullup resistor, typically greater than 500 , is required on scl if there are multiple masters on the bus, or if the single master has an open-drain scl output. series resistors in line with sda and scl are optional. series resistors protect the digital inputs of the MAX9867 from high-voltage spikes on the bus lines, and minimize crosstalk, and undershoot of the bus signals. bit transfer one data bit is transferred during each scl cycle. the data on sda must remain stable during the high period of the scl pulse. changes in sda while scl is high are control signals. see the start and stop conditions section. start and stop conditions sda and scl idle high when the bus is not in use. a master initiates communication by issuing a start con- dition. a start condition is a high-to-low transition on sda with scl high. a stop condition is a low-to-high transition on sda while scl is high (figure 10). a start condition from the master signals the beginning of a transmission to the MAX9867. the master terminates transmission, and frees the bus, by issuing a stop con- dition. the bus remains active if a repeated start condition is generated instead of a stop condition. scl sda t r t f t buf start condition stop condition repeated start condition start condition t su,sto t hd,sta t su,sta t hd,dat t su,dat t low t high t hd,sta t sp figure 9. 2-wire interface timing diagram scl sda ssrp figure 10. start, stop, and repeated start conditions
MAX9867 ultra-low power stereo audio codec ______________________________________________________________________________________ 47 early stop conditions the MAX9867 recognizes a stop condition at any point during data transmission except if the stop con- dition occurs in the same high pulse as a start condi- tion. for proper operation, do not send a stop condition during the same scl high pulse as the start condition. slave address the slave address is defined as the 7 most significant bits (msbs) followed by the read/write bit. for the MAX9867, the 7 most significant bits are 0011000. setting the read/write bit to 1 (slave address = 0x31) configures the MAX9867 for read mode. setting the read/write bit to 0 (slave address = 0x30) configures the MAX9867 for write mode. the address is the first byte of information sent to the MAX9867 after the start condition. acknowledge the acknowledge bit (ack) is a clocked 9th bit that the MAX9867 uses to handshake receipt each byte of data when in write mode (see figure 11). the MAX9867 pulls down sda during the entire master-generated 9th clock pulse if the previous byte is successfully received. monitoring ack allows for detection of unsuccessful data transfers. an unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. in the event of an unsuccessful data transfer, the bus master retries communication. the master pulls down sda during the 9th clock cycle to acknowledge receipt of data when the MAX9867 is in read mode. an acknowledge is sent by the master after each read byte to allow data transfer to continue. a not acknowledge is sent when the master reads the final byte of data from the MAX9867, followed by a stop condition. write data format a write to the MAX9867 includes transmission of a start condition, the slave address with the r/ w bit set to 0, 1 byte of data to configure the internal register address pointer, 1 or more bytes of data, and a stop condition. figure 12 illustrates the proper frame format for writing 1 byte of data to the MAX9867. figure 10 illustrates the frame format for writing n bytes of data to the MAX9867. a 0 slave address register address data byte acknowledge from MAX9867 r/w 1 byte autoincrement internal register address pointer acknowledge from MAX9867 acknowledge from MAX9867 b1 b0 b3 b2 b5 b4 b7 b6 s a a p figure 12. writing 1 byte of data to the MAX9867 1 scl start condition sda 28 9 clock pulse for acknowledgment acknowledge not acknowledge figure 11. acknowledge
MAX9867 ultra-low power stereo audio codec 48 ______________________________________________________________________________________ the slave address with the r/ w bit set to 0 indicates that the master intends to write data to the MAX9867. the MAX9867 acknowledges receipt of the address byte during the master-generated 9th scl pulse. the second byte transmitted from the master config- ures the MAX9867s internal register address pointer. the pointer tells the MAX9867 where to write the next byte of data. an acknowledge pulse is sent by the MAX9867 upon receipt of the address pointer data. the third byte sent to the MAX9867 contains the data that is written to the chosen register. an acknowledge pulse from the MAX9867 signals receipt of the data byte. the address pointer autoincrements to the next register address after each received data byte. this autoincre- ment feature allows a master to write to sequential regis- ters within one continuous frame. figure 13 illustrates how to write to multiple registers with one frame. the master signals the end of transmission by issuing a stop (p) condition. register addresses greater than 0x17 are reserved. do not write to these addresses. read data format send the slave address with the r/ w bit set to 1 to initi- ate a read operation. the MAX9867 acknowledges receipt of its slave address by pulling sda low during the 9th scl clock pulse. a start (s) command fol- lowed by a read command resets the address pointer to register 0x00. the first byte transmitted from the MAX9867 is the con- tent of register 0x00. transmitted data is valid on the rising edge of scl. the address pointer autoincre- ments after each read data byte. this autoincrement feature allows all registers to be read sequentially within one continuous frame. a stop condition can be issued after any number of read data bytes. if a stop condi- tion is issued followed by another read operation, the first data byte to be read is from register 0x00. the address pointer can be preset to a specific register before a read command is issued. the master presets the address pointer by first sending the MAX9867s slave address with the r/ w bit set to 0 followed by the register address. a repeated start (sr) condition is then sent followed by the slave address with the r/ w bit set to 1. the MAX9867 then transmits the contents of the specified register. the address pointer autoincre- ments after transmitting the first byte. the master acknowledges receipt of each read byte during the acknowledge clock pulse. the master must acknowledge all correctly received bytes except the last byte. the final byte must be followed by a not acknowledge from the master and then a stop condi- tion. figure 14 illustrates the frame format for reading 1 byte from the MAX9867. figure 15 illustrates the frame format for reading multiple bytes from the MAX9867. 1 byte autoincrement internal register address pointer acknowledge from MAX9867 acknowledge from MAX9867 b1 b0 b3 b2 b5 b4 b7 b6 a a 0 acknowledge from MAX9867 r/w s a 1 byte acknowledge from MAX9867 b1 b0 b3 b2 b5 b4 b7 b6 p a slave address register address data byte 1 data byte n figure 13. writing n bytes of data to the MAX9867 acknowledge from MAX9867 1 byte autoincrement internal register address pointer acknowledge from MAX9867 not acknowledge from master a a p a 0 acknowledge from MAX9867 r/w s r/w repeated start sr 1 slave address register address slave address data byte figure 14. reading 1 byte of data from the MAX9867
MAX9867 ultra-low power stereo audio codec ______________________________________________________________________________________ 49 acknowledge from MAX9867 1 byte autoincrement internal register address pointer acknowledge from MAX9867 a a ap 0 acknowledge from MAX9867 r/w s r/w repeated start sr 1 slave address register address slave address data byte figure 15. reading n bytes of data from the MAX9867 applications information proper layout and grounding are essential for optimum performance. when designing a pcb for the MAX9867, partition the circuitry so that the analog sections of the MAX9867 are separated from the digital sections. this ensures that the analog audio traces are not routed near digital traces. use a large continuous ground plane on a dedicated layer of the pcb to minimize loop areas. connect agnd and dgnd directly to the ground plane using the shortest trace length possible. proper grounding improves audio performance, minimizes crosstalk between channels, and prevents any digital noise from coupling into the analog audio signals. ground the bypass capacitors on micbias, reg, preg, and ref directly to the ground plane with mini- mum trace length. also be sure to minimize the path length to agnd. bypass avdd directly to agnd. connect all digital i/o termination to the ground plane with minimum path length to dgnd. bypass dvdd and dvddio directly to dgnd. route microphone signals from the microphone to the MAX9867 as a differential pair, ensuring that the posi- tive and negative signals follow the same path as close- ly as possible with equal trace length. when using single-ended microphones or other single-ended audio sources, ground the negative microphone input as near as possible to the audio source and then treat the posi- tive and negative traces as differential pairs. the MAX9867 tqfn package features an exposed thermal pad on its underside. connect the exposed thermal pad to agnd. an evaluation kit (ev kit) is available to provide an example layout for the MAX9867. the ev kit allows quick setup of the MAX9867 and includes easy-to-use software, allowing all internal registers to be controlled.
MAX9867 ultra-low power stereo audio codec 50 ______________________________________________________________________________________ mix vcm preg ref digital filtering digital audio interface linear reg clock gen i 2 c digital filtering adcl mxinl pgaml: +20db to 0db palen: 0/20/30db miclp/ digmicdata micln/ digmicclk dacl loutp loutn mix dmono mix digital filtering adcr dgnd () wlp package 1 (a2) pgnd 18 (e5) agnd 9 (a6) mxinr pgamr: +20db to 0db paren: 0/20/30db ligl: +24db to -6db avl: +3db to -12db avr: +3db to -12db 1 f 0.22 f 0.22 f 2.2k 2.2k 1 f 12 (c6) 1 f 8 (b5) 2.2 f 6 (b4) micbias ref reg 10 (b6) 11 (c5) micrp linl micrn 0.22 f 0.22 f 2.2k 2.2k 13 (c4) 0.47 f 15 (d5) ligr: +24db to -6db linr 0.47 f 16 (e6) 14 (d6) dacg: 0/6/12/18db mix dsts sdout 27 (d1) 28 (c2) 29 (c1) 30 (b1) bclk dvst: 0db to -60db daca: 0db to -15db dacg: 0/6/12/18db daca: 0db to -15db voll: +6db to -84db voll, lvolfix: +6db to -84db volr, lvolfix: +6db to -84db digital filtering dacr volr: +6db to -84db mix 22 (e3) 21 (d2) routp routn mix jack detect 19 (d3) jacksns/ aux 17 (d4) 20 (e4) sdin 31 (b2) mclk to processor to processor system clock 2 (b3) scl 3 (a3) sda 4 (c3) irq 26 (e1) dvddio 1.7v?3.6v lrclk 1 f 32 (a1) dvdd 1.8v 1 f 23 (e2) pvdd 1.8v 1 f 5 (a4) avdd 1.8v 1 f 7 (a5) preg MAX9867 functional diagram/typical operating circuit
MAX9867 ultra-low power stereo audio codec ______________________________________________________________________________________ 51 thin qfn (5mm 5mm) top view 29 30 28 27 12 11 13 scl irq avdd ref preg 14 dgnd pvdd loutn routn n.c. routp pgnd 12 sdin 4567 23 24 22 20 19 18 lrclk bclk micrn micrp miclp/digmicdata micln/digmicclk sda loutp 3 21 31 10 mclk micbias 32 9 dvdd agnd sdout 26 15 linl dvddio 25 16 linr reg jacksns/aux 8 17 n.c. + MAX9867 *ep *ep = exposed pad pin configurations top vi (bump sid do) dgd sda avdd dvdd 1 a b c d 234 wlp (2.2mm x 2.7mm) e preg agnd mclk scl ref bclk reg micbias sdin irq micrp lrclk micln miclp loutn routp jacksns sdout linl micrn pvdd loutp routn dvddio pgnd linr 56 MAX9867
MAX9867 ultra-low power stereo audio codec 52 ______________________________________________________________________________________ package type package code document no. 30 wlp w302a2+3 21-0211 32 tqfn-ep t3255+4 21-0140 package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . wlp pkg.eps
MAX9867 ultra-low power stereo audio codec ______________________________________________________________________________________ 53 package information (continued) for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . qfn thin.eps
MAX9867 ultra-low power stereo audio codec maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 54 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2009 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. package information (continued) for the latest package outline information and land patterns, go to www.maxim-ic.com/packages .

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